JP5511172B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5511172B2
JP5511172B2 JP2008261273A JP2008261273A JP5511172B2 JP 5511172 B2 JP5511172 B2 JP 5511172B2 JP 2008261273 A JP2008261273 A JP 2008261273A JP 2008261273 A JP2008261273 A JP 2008261273A JP 5511172 B2 JP5511172 B2 JP 5511172B2
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Prior art keywords
layer
semiconductor
semiconductor substrate
substrate
impurity
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Expired - Fee Related
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JP2008261273A
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English (en)
Japanese (ja)
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JP2009111371A5 (enExample
JP2009111371A (ja
Inventor
舜平 山崎
武司 志知
直樹 鈴木
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008261273A priority Critical patent/JP5511172B2/ja
Publication of JP2009111371A publication Critical patent/JP2009111371A/ja
Publication of JP2009111371A5 publication Critical patent/JP2009111371A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
JP2008261273A 2007-10-10 2008-10-08 半導体装置の作製方法 Expired - Fee Related JP5511172B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008261273A JP5511172B2 (ja) 2007-10-10 2008-10-08 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007264409 2007-10-10
JP2007264409 2007-10-10
JP2008261273A JP5511172B2 (ja) 2007-10-10 2008-10-08 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2009111371A JP2009111371A (ja) 2009-05-21
JP2009111371A5 JP2009111371A5 (enExample) 2011-11-17
JP5511172B2 true JP5511172B2 (ja) 2014-06-04

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Family Applications (1)

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JP2008261273A Expired - Fee Related JP5511172B2 (ja) 2007-10-10 2008-10-08 半導体装置の作製方法

Country Status (3)

Country Link
US (1) US8455331B2 (enExample)
JP (1) JP5511172B2 (enExample)
CN (1) CN101409223B (enExample)

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JP2010114431A (ja) * 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
KR101813460B1 (ko) 2009-12-18 2017-12-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US8476147B2 (en) * 2010-02-03 2013-07-02 Semiconductor Energy Laboratory Co., Ltd. SOI substrate and manufacturing method thereof
CN106449649B (zh) * 2010-03-08 2019-09-27 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法
TWI463233B (zh) * 2011-04-13 2014-12-01 Color electronic paper structure and manufacturing method thereof
JP6083150B2 (ja) * 2012-08-21 2017-02-22 富士通セミコンダクター株式会社 半導体装置の製造方法
KR101476747B1 (ko) * 2013-05-30 2014-12-26 전북대학교산학협력단 갈륨함유 반도체 소자의 제조방법
TWI656633B (zh) * 2014-02-28 2019-04-11 日商半導體能源研究所股份有限公司 顯示裝置的製造方法及電子裝置的製造方法
US9548371B2 (en) * 2014-04-23 2017-01-17 Globalfoundries Singapore Pte. Ltd. Integrated circuits having nickel silicide contacts and methods for fabricating the same
KR102426960B1 (ko) * 2015-10-15 2022-08-01 주식회사 테스 플라즈마를 이용하여 실리콘 산화막을 형성하는 방법
US11167375B2 (en) 2018-08-10 2021-11-09 The Research Foundation For The State University Of New York Additive manufacturing processes and additively manufactured products
US10553474B1 (en) 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate
CN116195075A (zh) * 2020-09-17 2023-05-30 日亚化学工业株式会社 图像显示装置的制造方法及图像显示装置
CN114795222B (zh) * 2022-05-05 2025-08-29 苏州博志金钻科技有限责任公司 一种具有绝缘薄膜的微针阵列电极及其制备方法
CN120600622B (zh) * 2025-05-29 2025-12-02 西安电子科技大学 基于倒置转移技术的N面GaN基外延结构及其制备方法

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Also Published As

Publication number Publication date
US20090098674A1 (en) 2009-04-16
CN101409223B (zh) 2013-06-12
JP2009111371A (ja) 2009-05-21
CN101409223A (zh) 2009-04-15
US8455331B2 (en) 2013-06-04

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