JP5511172B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5511172B2
JP5511172B2 JP2008261273A JP2008261273A JP5511172B2 JP 5511172 B2 JP5511172 B2 JP 5511172B2 JP 2008261273 A JP2008261273 A JP 2008261273A JP 2008261273 A JP2008261273 A JP 2008261273A JP 5511172 B2 JP5511172 B2 JP 5511172B2
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Japan
Prior art keywords
layer
semiconductor
semiconductor substrate
substrate
impurity
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Expired - Fee Related
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JP2008261273A
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English (en)
Japanese (ja)
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JP2009111371A (ja
JP2009111371A5 (enExample
Inventor
舜平 山崎
武司 志知
直樹 鈴木
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008261273A priority Critical patent/JP5511172B2/ja
Publication of JP2009111371A publication Critical patent/JP2009111371A/ja
Publication of JP2009111371A5 publication Critical patent/JP2009111371A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
JP2008261273A 2007-10-10 2008-10-08 半導体装置の作製方法 Expired - Fee Related JP5511172B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008261273A JP5511172B2 (ja) 2007-10-10 2008-10-08 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007264409 2007-10-10
JP2007264409 2007-10-10
JP2008261273A JP5511172B2 (ja) 2007-10-10 2008-10-08 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2009111371A JP2009111371A (ja) 2009-05-21
JP2009111371A5 JP2009111371A5 (enExample) 2011-11-17
JP5511172B2 true JP5511172B2 (ja) 2014-06-04

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Family Applications (1)

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JP2008261273A Expired - Fee Related JP5511172B2 (ja) 2007-10-10 2008-10-08 半導体装置の作製方法

Country Status (3)

Country Link
US (1) US8455331B2 (enExample)
JP (1) JP5511172B2 (enExample)
CN (1) CN101409223B (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7877895B2 (en) * 2006-06-26 2011-02-01 Tokyo Electron Limited Substrate processing apparatus
JP4992975B2 (ja) * 2008-06-16 2012-08-08 東レ株式会社 パターニング方法およびこれを用いたデバイスの製造方法ならびにデバイス
JP2010114431A (ja) * 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
EP2513966B1 (en) * 2009-12-18 2020-09-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8476147B2 (en) * 2010-02-03 2013-07-02 Semiconductor Energy Laboratory Co., Ltd. SOI substrate and manufacturing method thereof
CN110718557B (zh) * 2010-03-08 2023-12-26 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法
TWI463233B (zh) * 2011-04-13 2014-12-01 Color electronic paper structure and manufacturing method thereof
JP6083150B2 (ja) * 2012-08-21 2017-02-22 富士通セミコンダクター株式会社 半導体装置の製造方法
KR101476747B1 (ko) * 2013-05-30 2014-12-26 전북대학교산학협력단 갈륨함유 반도체 소자의 제조방법
TWI696023B (zh) * 2014-02-28 2020-06-11 日商半導體能源研究所股份有限公司 顯示裝置的製造方法及電子裝置的製造方法
US9548371B2 (en) * 2014-04-23 2017-01-17 Globalfoundries Singapore Pte. Ltd. Integrated circuits having nickel silicide contacts and methods for fabricating the same
KR102426960B1 (ko) * 2015-10-15 2022-08-01 주식회사 테스 플라즈마를 이용하여 실리콘 산화막을 형성하는 방법
US11426818B2 (en) 2018-08-10 2022-08-30 The Research Foundation for the State University Additive manufacturing processes and additively manufactured products
US10553474B1 (en) 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate
JP7669643B2 (ja) * 2020-09-17 2025-04-30 日亜化学工業株式会社 画像表示装置の製造方法および画像表示装置
CN114795222B (zh) * 2022-05-05 2025-08-29 苏州博志金钻科技有限责任公司 一种具有绝缘薄膜的微针阵列电极及其制备方法
CN120600622B (zh) * 2025-05-29 2025-12-02 西安电子科技大学 基于倒置转移技术的N面GaN基外延结构及其制备方法

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5064775A (en) 1990-09-04 1991-11-12 Industrial Technology Research Institute Method of fabricating an improved polycrystalline silicon thin film transistor
US5104818A (en) 1991-04-15 1992-04-14 United Technologies Corporation Preimplanted N-channel SOI mesa
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2873660B2 (ja) 1994-01-08 1999-03-24 株式会社半導体エネルギー研究所 半導体集積回路の作製方法
JP4026182B2 (ja) 1995-06-26 2007-12-26 セイコーエプソン株式会社 半導体装置の製造方法、および電子機器の製造方法
TW313674B (en) * 1996-09-21 1997-08-21 United Microelectronics Corp High pressure metal oxide semiconductor device and manufacturing method thereof
JP4103968B2 (ja) * 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
US6534409B1 (en) * 1996-12-04 2003-03-18 Micron Technology, Inc. Silicon oxide co-deposition/etching process
FR2758907B1 (fr) * 1997-01-27 1999-05-07 Commissariat Energie Atomique Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique
US6191007B1 (en) 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
US6548382B1 (en) 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6388652B1 (en) * 1997-08-20 2002-05-14 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device
US6686623B2 (en) * 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
JP3849683B2 (ja) * 1998-02-25 2006-11-22 セイコーエプソン株式会社 薄膜トランジスタの剥離方法
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP3951487B2 (ja) * 1998-12-25 2007-08-01 信越半導体株式会社 Ｓｏｉ基板及びその製造方法
US6362078B1 (en) * 1999-02-26 2002-03-26 Intel Corporation Dynamic threshold voltage device and methods for fabricating dynamic threshold voltage devices
JP2000332021A (ja) * 1999-05-18 2000-11-30 Hitachi Ltd Ｓｏｉ基板およびその製造方法ならびに半導体装置およびその製造方法
US6583440B2 (en) * 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
JP2003257992A (ja) 2002-03-06 2003-09-12 Matsushita Electric Ind Co Ltd 薄膜トランジスタの製造方法
US6908797B2 (en) 2002-07-09 2005-06-21 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
TWI330269B (en) * 2002-12-27 2010-09-11 Semiconductor Energy Lab Separating method
JP4319078B2 (ja) * 2004-03-26 2009-08-26 シャープ株式会社 半導体装置の製造方法
JP5113999B2 (ja) * 2004-09-28 2013-01-09 シャープ株式会社 水素イオン注入剥離方法
FR2876219B1 (fr) * 2004-10-06 2006-11-24 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
JP3998677B2 (ja) * 2004-10-19 2007-10-31 株式会社東芝 半導体ウェハの製造方法
JPWO2006117900A1 (ja) * 2005-04-26 2008-12-18 シャープ株式会社 半導体装置の製造方法及び半導体装置
KR101299604B1 (ko) * 2005-10-18 2013-08-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제조 방법
US7456080B2 (en) * 2005-12-19 2008-11-25 Corning Incorporated Semiconductor on glass insulator made using improved ion implantation process
EP2002484A4 (en) 2006-04-05 2016-06-08 Silicon Genesis Corp METHOD AND STRUCTURE FOR THE MANUFACTURE OF SOLAR CELLS BY LAYER TRANSFER METHOD
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
EP1975998A3 (en) * 2007-03-26 2013-12-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a plurality of island-shaped SOI structures
EP1978554A3 (en) * 2007-04-06 2011-10-12 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate comprising implantation and separation steps

Also Published As

Publication number Publication date
US8455331B2 (en) 2013-06-04
US20090098674A1 (en) 2009-04-16
JP2009111371A (ja) 2009-05-21
CN101409223A (zh) 2009-04-15
CN101409223B (zh) 2013-06-12

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