JP5509599B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
JP5509599B2
JP5509599B2 JP2009012955A JP2009012955A JP5509599B2 JP 5509599 B2 JP5509599 B2 JP 5509599B2 JP 2009012955 A JP2009012955 A JP 2009012955A JP 2009012955 A JP2009012955 A JP 2009012955A JP 5509599 B2 JP5509599 B2 JP 5509599B2
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JP
Japan
Prior art keywords
cell
gate
metal wiring
formation region
gate pad
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Expired - Fee Related
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JP2009012955A
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English (en)
Japanese (ja)
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JP2010171243A (ja
JP2010171243A5 (enExample
Inventor
周祐 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2009012955A priority Critical patent/JP5509599B2/ja
Priority to US12/588,938 priority patent/US7919793B2/en
Priority to CN2010101038722A priority patent/CN101794774B/zh
Publication of JP2010171243A publication Critical patent/JP2010171243A/ja
Publication of JP2010171243A5 publication Critical patent/JP2010171243A5/ja
Application granted granted Critical
Publication of JP5509599B2 publication Critical patent/JP5509599B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

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  • Design And Manufacture Of Integrated Circuits (AREA)
JP2009012955A 2009-01-23 2009-01-23 半導体集積回路 Expired - Fee Related JP5509599B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009012955A JP5509599B2 (ja) 2009-01-23 2009-01-23 半導体集積回路
US12/588,938 US7919793B2 (en) 2009-01-23 2009-11-03 Semiconductor integrated circuit
CN2010101038722A CN101794774B (zh) 2009-01-23 2010-01-25 半导体集成电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009012955A JP5509599B2 (ja) 2009-01-23 2009-01-23 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2010171243A JP2010171243A (ja) 2010-08-05
JP2010171243A5 JP2010171243A5 (enExample) 2012-01-19
JP5509599B2 true JP5509599B2 (ja) 2014-06-04

Family

ID=42353457

Family Applications (1)

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JP2009012955A Expired - Fee Related JP5509599B2 (ja) 2009-01-23 2009-01-23 半導体集積回路

Country Status (3)

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US (1) US7919793B2 (enExample)
JP (1) JP5509599B2 (enExample)
CN (1) CN101794774B (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5552775B2 (ja) 2009-08-28 2014-07-16 ソニー株式会社 半導体集積回路
CN102129493B (zh) * 2011-03-02 2013-03-06 福州瑞芯微电子有限公司 数字ic设计流程中实现自动化eco网表的方法
KR20130031036A (ko) 2011-09-20 2013-03-28 삼성전자주식회사 Ｅｃｏ 논리 셀 및 ｅｃｏ 논리 셀을 이용한 설계 변경 방법
US9831230B2 (en) * 2013-08-13 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
KR102419644B1 (ko) * 2015-10-26 2022-07-11 삼성전자주식회사 Eco 셀, 그것의 레이아웃 및 eco 셀을 포함하는 집적 회로
JPWO2017145906A1 (ja) * 2016-02-25 2018-12-27 株式会社ソシオネクスト 半導体集積回路装置
US10846452B2 (en) * 2016-07-01 2020-11-24 Globalfoundries Inc. Method, apparatus and system for wide metal line for SADP routing
US9634026B1 (en) 2016-07-13 2017-04-25 Qualcomm Incorporated Standard cell architecture for reduced leakage current and improved decoupling capacitance
US11488947B2 (en) * 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
US11270992B2 (en) * 2019-11-05 2022-03-08 Samsung Electronics Co., Ltd. Semiconductor devices
US11488948B2 (en) * 2020-03-30 2022-11-01 Samsung Electronics Co., Ltd. Semiconductor devices, layout design methods for the same, and methods for fabricating the same
CN114664725B (zh) * 2020-12-23 2025-07-29 华润微电子（重庆）有限公司 GaN器件互联结构及其制备方法
CN113161346B (zh) * 2021-03-17 2022-04-01 长鑫存储技术有限公司 集成电路及其布局方法
US11868697B2 (en) * 2021-08-27 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd Base layout cell
US12205894B2 (en) * 2022-03-17 2025-01-21 Macronix International Co., Ltd. Routing pattern

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828485B2 (ja) * 1988-06-20 1996-03-21 日本電信電話株式会社 相補型ｍｉｓマスタスライスｌｓｉの基本セル
JP3130918B2 (ja) * 1990-10-31 2001-01-31 富士通株式会社 設計変更用セル及びこれを用いたレイアウト方法
JP3060673B2 (ja) * 1991-11-13 2000-07-10 日本電気株式会社 半導体集積回路
JP3152642B2 (ja) * 1998-01-29 2001-04-03 三洋電機株式会社 半導体集積回路装置
JP4620942B2 (ja) * 2003-08-21 2011-01-26 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク
JP2006269900A (ja) 2005-03-25 2006-10-05 Yamaha Corp 半導体集積回路の設計方法
JP2007141971A (ja) * 2005-11-15 2007-06-07 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法
US7562326B2 (en) * 2007-08-09 2009-07-14 United Microelectronics Corp. Method of generating a standard cell layout and transferring the standard cell layout to a substrate

Also Published As

Publication number Publication date
CN101794774B (zh) 2012-03-21
US7919793B2 (en) 2011-04-05
JP2010171243A (ja) 2010-08-05
CN101794774A (zh) 2010-08-04
US20100187573A1 (en) 2010-07-29

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