JP5478166B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5478166B2
JP5478166B2 JP2009207362A JP2009207362A JP5478166B2 JP 5478166 B2 JP5478166 B2 JP 5478166B2 JP 2009207362 A JP2009207362 A JP 2009207362A JP 2009207362 A JP2009207362 A JP 2009207362A JP 5478166 B2 JP5478166 B2 JP 5478166B2
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JP
Japan
Prior art keywords
film
insulating film
semiconductor
substrate
semiconductor film
Prior art date
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Expired - Fee Related
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JP2009207362A
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English (en)
Japanese (ja)
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JP2010093241A (ja
JP2010093241A5 (enExample
Inventor
一哉 花岡
崇史 新宮
太一 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2009207362A priority Critical patent/JP5478166B2/ja
Publication of JP2010093241A publication Critical patent/JP2010093241A/ja
Publication of JP2010093241A5 publication Critical patent/JP2010093241A5/ja
Application granted granted Critical
Publication of JP5478166B2 publication Critical patent/JP5478166B2/ja
Expired - Fee Related legal-status Critical Current
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Classifications

    • H10P90/1916—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H10W10/181—

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009207362A 2008-09-11 2009-09-08 半導体装置の作製方法 Expired - Fee Related JP5478166B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009207362A JP5478166B2 (ja) 2008-09-11 2009-09-08 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008233270 2008-09-11
JP2008233270 2008-09-11
JP2009207362A JP5478166B2 (ja) 2008-09-11 2009-09-08 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2010093241A JP2010093241A (ja) 2010-04-22
JP2010093241A5 JP2010093241A5 (enExample) 2012-09-06
JP5478166B2 true JP5478166B2 (ja) 2014-04-23

Family

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Family Applications (1)

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JP2009207362A Expired - Fee Related JP5478166B2 (ja) 2008-09-11 2009-09-08 半導体装置の作製方法

Country Status (2)

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US (1) US8415228B2 (enExample)
JP (1) JP5478166B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120042365A (ko) * 2010-10-25 2012-05-03 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
TWI570809B (zh) * 2011-01-12 2017-02-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
JPWO2012124281A1 (ja) * 2011-03-11 2014-07-17 シャープ株式会社 薄膜トランジスタ基板の製造方法およびその方法により製造された薄膜トランジスタ基板、表示装置
JP6032963B2 (ja) * 2012-06-20 2016-11-30 キヤノン株式会社 Ｓｏｉ基板、ｓｏｉ基板の製造方法および半導体装置の製造方法
US8717202B1 (en) * 2013-03-14 2014-05-06 Aimpad, LLC Force sensitive input devices and methods
CN103928499A (zh) * 2014-04-22 2014-07-16 西安神光皓瑞光电科技有限公司 一种缓冲型衬底结构及其上的侧向外延生长方法
TWI755773B (zh) 2014-06-30 2022-02-21 日商半導體能源研究所股份有限公司 發光裝置，模組，及電子裝置
JP6784031B2 (ja) 2016-02-15 2020-11-11 セイコーエプソン株式会社 電気光学装置、電気光学装置の製造方法、および電子機器
US10515905B1 (en) * 2018-06-18 2019-12-24 Raytheon Company Semiconductor device with anti-deflection layers
US11061482B2 (en) 2019-01-04 2021-07-13 Aimpad, LLC Force sensitive input devices and methods

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* Cited by examiner, † Cited by third party
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CA2061796C (en) * 1991-03-28 2002-12-24 Kalluri R. Sarma High mobility integrated drivers for active matrix displays
US6146970A (en) * 1998-05-26 2000-11-14 Motorola Inc. Capped shallow trench isolation and method of formation
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7235810B1 (en) * 1998-12-03 2007-06-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US7245018B1 (en) * 1999-06-22 2007-07-17 Semiconductor Energy Laboratory Co., Ltd. Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
US6797632B1 (en) * 1999-10-14 2004-09-28 Shin-Etsu Handotai Co., Ltd. Bonded wafer producing method and bonded wafer
JP4776752B2 (ja) * 2000-04-19 2011-09-21 ルネサスエレクトロニクス株式会社 半導体装置
JP4831885B2 (ja) * 2001-04-27 2011-12-07 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
US6949451B2 (en) * 2003-03-10 2005-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. SOI chip with recess-resistant buried insulator and method of manufacturing the same
JP2004281878A (ja) 2003-03-18 2004-10-07 Seiko Epson Corp 半導体基板の製造方法及びこれにより製造される半導体基板、電気光学装置並びに電子機器
JP2005044864A (ja) * 2003-07-23 2005-02-17 Seiko Epson Corp 複合半導体基板の製造方法、複合半導体基板、デバイスの製造方法、デバイス、電気光学装置並びに電子機器
US7402520B2 (en) * 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
JP4963175B2 (ja) * 2005-11-21 2012-06-27 株式会社半導体エネルギー研究所 半導体装置の製造方法、半導体装置、及び電子機器
JP2007317988A (ja) * 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
US7755113B2 (en) * 2007-03-16 2010-07-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, semiconductor display device, and manufacturing method of semiconductor device
WO2008123116A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
US7846817B2 (en) * 2007-03-26 2010-12-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
JP2007201502A (ja) * 2007-04-20 2007-08-09 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
FR2920912B1 (fr) * 2007-09-12 2010-08-27 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure par transfert de couche

Also Published As

Publication number Publication date
US20100062583A1 (en) 2010-03-11
JP2010093241A (ja) 2010-04-22
US8415228B2 (en) 2013-04-09

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