JP5470311B2 - トレンチにより制限された分離拡散領域を備えた相補型アナログバイポーラトランジスタ - Google Patents
トレンチにより制限された分離拡散領域を備えた相補型アナログバイポーラトランジスタ Download PDFInfo
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Description
この発明は、接合−分離型集積回路素子のための分離構造に関し、特に相補型アナログバイポーラ(CAB)トランジスタとこれを形成する方法とに関する。
集積回路の最小限のパターンサイズが小さくなると、集積回路(IC)チップ上の素子の記録密度を高めることが必要になる。素子間の距離を同様に短くすることができなければ、より小さい素子の利点が大幅に損なわれる。
この発明に従うと、熱拡散プロセス中のドーパントの横方向の拡散は、(拡散前に)拡散の一つの側またはいくつかの側にトレンチを形成し、トレンチに酸化物または他の誘電材料を充填することによって制限される。好ましくは、ドーパントの横方向の拡散は、ドーパントの2つまたはそれ以上の側上、特にプロセスにおいてより深く拡散した接合上にトレンチを形成することによっていくつかの方向に制限される。
この発明の別の局面に従うと、誘電体が充填されたトレンチがエピタキシャル層または基板の表面から埋もれた領域へと延在する。この埋もれた領域は、エピタキシャル層と比較的高いエネルギで基板にドーパントを注入することによって形成される深い領域の基板との間の界面において形成される埋込層であってもよい。
図12は、この発明の構造およびプロセスの基本的な例を示す。Nエピ層402はP基板400上に成長し、ホウ素などのP型のドーパントがNエピ層402の上面を通じて注入されてP分離領域404を形成する。トレンチ408Aおよび408BはP領域404の両側のNエピ層402に形成されている。トレンチ408Aおよび40Bは、酸化物、窒化物または異なる種類の誘電体でできた多重層であり得る誘電材料406が充填される。
エミッタ: P+領域646
ベース: Nベース領域632およびNエピ層616の一部分
コレクタ: P埋込層614CおよびP分離領域630B
垂直なPNPトランジスタ660は、N埋込層608AおよびNシンカ626Cを含む分離構造によってP基板600から分離される。
エミッタ: P+領域642
ベース: Pベース領域638
コレクタ: Nエピ層616の一部分、N埋込層608B、Nシンカ626F
ラテラルPNPトランジスタ664は以下の領域を含む:
エミッタ: P分離領域630I′
ベース: Nエピ層616の一部分、N埋込層608C、Nシンカ626H
コレクタ: P分離領域630I
加えて、垂直なPNPトランジスタ660は、P分離領域630DおよびP埋込層614Aを含む垂直な柱によって垂直なNPNトランジスタ662から分離される。垂直なNPNトランジスタ662は、P分離領域630GおよびP埋込層614Bを含む垂直な柱によってラテラルPNPトランジスタ664から分離される。
Claims (14)
- 半導体構造であって、
半導体基板と、
前記基板の上に形成されるエピタキシャル層とを含み、前記エピタキシャル層は背景ドーピング濃度を有し、前記半導体構造はさらに、
第1および第2のトレンチを含み、前記第1および第2のトレンチは、前記第1のトレンチと前記第2のトレンチとの間にメサを規定するように前記エピタキシャル層の表面から下方に延在し、前記第1および第2のトレンチの各々の底部は前記エピタキシャル層に位置し、前記トレンチの各々は、実質的に誘電材料が充填されており、前記半導体構造はさらに、
前記第1のトレンチと前記第2のトレンチとの間の位置において、前記エピタキシャル層の前記表面から前記基板へと下方に延在するドーパントのウェルを含み、前記ウェルは、前記エピタキシャル層の前記背景ドーピング濃度とは異なるドーピング濃度を有し、前記ウェルは、前記エピタキシャル層の残りの部分と第1および第2の接合を形成し、前記第1の接合は、前記第1のトレンチの底部から前記基板に延在し、前記第2の接合は、前記第2のトレンチの底部から前記基板に延在し、
前記ウェルは第1の導電型の材料でドープされ、前記基板および前記エピタキシャル層は、前記第1の導電型とは反対の第2の導電型の材料でドープされ、前記第1および第2の接合はPN接合である、半導体構造。 - 前記ウェルおよび前記第1および第2のトレンチは分離構造を構成し、前記分離構造は、前記分離構造の一方側の前記エピタキシャル層に形成された第1の素子と前記分離構造の他方側の前記エピタキシャル層に形成された第2の素子とを電気的に分離し、
前記分離構造による電気的分離は前記第1および第2のトレンチとPN接合とによってもたらされる、請求項1に記載の半導体構造。 - 前記ウェルが前記メサを占める、請求項1または請求項2に記載の半導体構造。
- 前記ウェルは前記第1の導電型の埋込層を含み、前記埋込層は、前記基板から上方に延在し、前記ウェルの残りの部分と融合する、請求項1または請求項2に記載の半導体構造。
- 前記埋込層は、前記第1および第2のトレンチの各々の前記底部のレベルよりも下の前記エピタキシャル層におけるレベルで前記ウェルの前記残りの部分と融合する、請求項4に記載の半導体構造。
- 前記第1および第2のトレンチは、前記エピタキシャル層の厚さの10%〜90%にまで延在する、請求項1または請求項2に記載の半導体構造。
- 前記第1および第2のトレンチは、前記エピタキシャル層の前記厚さの30%〜70%にまで延在する、請求項6に記載の半導体構造。
- 前記第1および第2のトレンチは、前記エピタキシャル層の前記厚さの半分まで延在する、請求項7に記載の半導体構造。
- 前記誘電材料は酸化物を含む、請求項1または請求項2に記載の半導体構造。
- 前記誘電材料は窒化物を含む、請求項1または請求項2に記載の半導体構造。
- 前記第1および第2のトレンチは0.1μm〜2μmの幅である、請求項1または請求項2に記載の半導体構造。
- 半導体構造を作製する方法であって、
第2の導電型の材料でドープされた半導体基板を設けるステップと、
前記基板の上に、第2の導電型の材料でドープされ、かつ背景ドーピング濃度を有するエピタキシャル層を形成するステップと、
前記エピタキシャル層の表面から下方に延在するように第1および第2のトレンチを形成するステップとを備え、
前記第1および第2のトレンチは、前記第1および第2のトレンチの間にメサを規定するように、かつ前記第1および第2のトレンチの各々の底部が前記エピタキシャル層に位置するように形成され、さらに
前記第1および第2のトレンチに実質的に誘電材料を充填するステップと、
素子同士を互いに電気的に分離するウェルを形成するために、前記誘電材料を充填された前記第1および第2のトレンチ間における前記メサに、前記第2の導電型とは反対の第1の導電型のドーパントを導入するステップとを備え、
前記ウェルは、前記エピタキシャル層の前記表面から下方に延在するように、かつ前記エピタキシャル層の前記背景ドーピング濃度とは異なるドーピング濃度を有するように、かつ前記エピタキシャル層の残りの部分と第1および第2の接合を形成するように形成され、
前記第1の接合は前記第1のトレンチの底部から下方に延在するように、前記第2の接合は前記第2のトレンチの底部から下方に延在するように形成され、
前記ウェルおよび前記第1および第2のトレンチは分離構造を構成し、前記分離構造は、前記分離構造の一方側の前記エピタキシャル層に形成された第1の素子と前記分離構造の他方側の前記エピタキシャル層に形成された第2の素子とを電気的に分離し、
前記分離構造による電気的分離は前記第1および第2のトレンチとPN接合とによってもたらされ、
前記第1および第2の接合はPN接合である、方法。 - 前記エピタキシャル層において前記ドーパントを前記エピタキシャル層の前記表面から前記基板へと下方に拡散させるように前記基板を加熱するステップを含む、請求項12に記載の方法。
- 前記基板から上方に延在するように埋込層を形成するステップをさらに備え、
前記ウェルは前記埋込層の上に形成され、さらに
前記基板を加熱して、前記埋込層を前記ウェルに達するまで上方に拡散させるステップを備えた、請求項12または13に記載の方法。
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