JP5467458B2 - 半導体デバイス及び部品のパッケージ化装置、半導体デバイス及び部品のパッケージ化方法 - Google Patents

半導体デバイス及び部品のパッケージ化装置、半導体デバイス及び部品のパッケージ化方法 Download PDF

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JP5467458B2
JP5467458B2 JP2009553715A JP2009553715A JP5467458B2 JP 5467458 B2 JP5467458 B2 JP 5467458B2 JP 2009553715 A JP2009553715 A JP 2009553715A JP 2009553715 A JP2009553715 A JP 2009553715A JP 5467458 B2 JP5467458 B2 JP 5467458B2
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die
board
interconnect
backside
array
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JP2010521818A (ja
JP2010521818A5 (https=
Inventor
ジェイ． コリシス，デイビッド
ブルックス，ジェイ．マイケル
クアン リー，チュン
ホイ チョン，チン
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マイクロン テクノロジー， インク．
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
    • Y10T29/53183—Multilead component

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
JP2009553715A 2007-03-12 2008-03-10 半導体デバイス及び部品のパッケージ化装置、半導体デバイス及び部品のパッケージ化方法 Active JP5467458B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SG200701790-8A SG146460A1 (en) 2007-03-12 2007-03-12 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
SG200701790-8 2007-03-12
PCT/US2008/056424 WO2008112643A2 (en) 2007-03-12 2008-03-10 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components

Publications (3)

Publication Number Publication Date
JP2010521818A JP2010521818A (ja) 2010-06-24
JP2010521818A5 JP2010521818A5 (https=) 2011-05-06
JP5467458B2 true JP5467458B2 (ja) 2014-04-09

Family

ID=39760341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009553715A Active JP5467458B2 (ja) 2007-03-12 2008-03-10 半導体デバイス及び部品のパッケージ化装置、半導体デバイス及び部品のパッケージ化方法

Country Status (8)

Country Link
US (2) US7759785B2 (https=)
EP (1) EP2130224B1 (https=)
JP (1) JP5467458B2 (https=)
KR (1) KR101407773B1 (https=)
CN (1) CN101632175B (https=)
SG (1) SG146460A1 (https=)
TW (1) TWI374536B (https=)
WO (1) WO2008112643A2 (https=)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG146460A1 (en) * 2007-03-12 2008-10-30 Micron Technology Inc Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
TW200908260A (en) * 2007-08-08 2009-02-16 Phoenix Prec Technology Corp Packaging substrate and application thereof
US20090194871A1 (en) 2007-12-27 2009-08-06 Utac - United Test And Assembly Test Center, Ltd. Semiconductor package and method of attaching semiconductor dies to substrates
SG142321A1 (en) 2008-04-24 2009-11-26 Micron Technology Inc Pre-encapsulated cavity interposer
JP5543094B2 (ja) * 2008-10-10 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 低ノイズ半導体パッケージ
US7923290B2 (en) * 2009-03-27 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system having dual sided connection and method of manufacture thereof
JP5215244B2 (ja) * 2009-06-18 2013-06-19 新光電気工業株式会社 半導体装置
US8310835B2 (en) * 2009-07-14 2012-11-13 Apple Inc. Systems and methods for providing vias through a modular component
TWI508239B (zh) * 2009-08-20 2015-11-11 精材科技股份有限公司 晶片封裝體及其形成方法
KR101221869B1 (ko) * 2009-08-31 2013-01-15 한국전자통신연구원 반도체 패키지 및 그 제조 방법
CN102237324A (zh) * 2010-04-29 2011-11-09 国碁电子(中山)有限公司 集成电路封装结构及方法
TWI416679B (zh) 2010-12-06 2013-11-21 財團法人工業技術研究院 半導體結構及其製造方法
US8558369B2 (en) * 2011-03-25 2013-10-15 Stats Chippac Ltd. Integrated circuit packaging system with interconnects and method of manufacture thereof
US9281260B2 (en) 2012-03-08 2016-03-08 Infineon Technologies Ag Semiconductor packages and methods of forming the same
CN104067387B (zh) * 2012-03-22 2016-12-14 三菱电机株式会社 半导体装置及其制造方法
US8860202B2 (en) * 2012-08-29 2014-10-14 Macronix International Co., Ltd. Chip stack structure and manufacturing method thereof
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
JP5846187B2 (ja) * 2013-12-05 2016-01-20 株式会社村田製作所 部品内蔵モジュール
US20150221570A1 (en) * 2014-02-04 2015-08-06 Amkor Technology, Inc. Thin sandwich embedded package
US9443744B2 (en) * 2014-07-14 2016-09-13 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
US9515017B2 (en) * 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
US9230900B1 (en) * 2014-12-18 2016-01-05 Intel Corporation Ground via clustering for crosstalk mitigation
US9397078B1 (en) * 2015-03-02 2016-07-19 Micron Technology, Inc. Semiconductor device assembly with underfill containment cavity
CN105390477B (zh) * 2015-12-11 2018-08-17 苏州捷研芯纳米科技有限公司 一种多芯片3d二次封装半导体器件及其封装方法
US10388636B2 (en) 2015-12-21 2019-08-20 Intel Corporation Integrating system in package (SIP) with input/output (IO) board for platform miniaturization
CN106098676A (zh) * 2016-08-15 2016-11-09 黄卫东 多通道堆叠封装结构及封装方法
US10229859B2 (en) * 2016-08-17 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
KR102647213B1 (ko) 2016-12-31 2024-03-15 인텔 코포레이션 전자 디바이스 패키지
US10319684B2 (en) * 2017-04-11 2019-06-11 STATS ChipPAC Pte. Ltd. Dummy conductive structures for EMI shielding
JP7003439B2 (ja) * 2017-04-27 2022-01-20 富士電機株式会社 半導体装置
US10403602B2 (en) 2017-06-29 2019-09-03 Intel IP Corporation Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory
US10529592B2 (en) * 2017-12-04 2020-01-07 Micron Technology, Inc. Semiconductor device assembly with pillar array
US11257803B2 (en) * 2018-08-25 2022-02-22 Octavo Systems Llc System in a package connectors
DE102020206769B3 (de) * 2020-05-29 2021-06-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein Mikroelektronische anordnung und verfahren zur herstellung derselben
US11776888B2 (en) * 2021-05-28 2023-10-03 Qualcomm Incorporated Package with a substrate comprising protruding pad interconnects

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5861670A (en) * 1979-10-04 1999-01-19 Fujitsu Limited Semiconductor device package
JPH0719970B2 (ja) 1988-05-09 1995-03-06 日本電気株式会社 多層印刷配線板の製造方法
JP2681292B2 (ja) 1988-12-24 1997-11-26 イビデン電子工業株式会社 多層プリント配線板
US5043794A (en) * 1990-09-24 1991-08-27 At&T Bell Laboratories Integrated circuit package and compact assemblies thereof
JP2516489B2 (ja) 1991-05-22 1996-07-24 住友軽金属工業株式会社 力センサ及び力測定装置
JP3026126B2 (ja) 1991-12-13 2000-03-27 日本ミクロン株式会社 削り出しによるチップキャリア
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
JPH09199526A (ja) * 1996-01-18 1997-07-31 Hitachi Ltd 半導体装置
JPH1056109A (ja) * 1996-08-12 1998-02-24 Hitachi Ltd 半導体装置
KR100240748B1 (ko) * 1996-12-30 2000-01-15 윤종용 기판을 갖는 반도체 칩 패키지와 그 제조 방법 및 그를 이용한적층 패키지
JPH1167963A (ja) * 1997-08-26 1999-03-09 Matsushita Electric Works Ltd 半導体装置
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
JP3398721B2 (ja) * 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
TW472330B (en) * 1999-08-26 2002-01-11 Toshiba Corp Semiconductor device and the manufacturing method thereof
JP2001144218A (ja) * 1999-11-17 2001-05-25 Sony Corp 半導体装置及び半導体装置の製造方法
JP2001177051A (ja) * 1999-12-20 2001-06-29 Toshiba Corp 半導体装置及びシステム装置
JP2001291800A (ja) * 2000-04-10 2001-10-19 Nippon Micron Kk 電子部品用パッケージ
US7132841B1 (en) * 2000-06-06 2006-11-07 International Business Machines Corporation Carrier for test, burn-in, and first level packaging
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
JP2002237682A (ja) 2001-02-08 2002-08-23 Cmk Corp 部品実装用凹部を備えた多層プリント配線板及びその製造方法
US6717061B2 (en) * 2001-09-07 2004-04-06 Irvine Sensors Corporation Stacking of multilayer modules
WO2003067656A1 (en) 2002-02-06 2003-08-14 Ibiden Co., Ltd. Semiconductor chip mounting board, its manufacturing method, and semiconductor module
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
DE10320579A1 (de) * 2003-05-07 2004-08-26 Infineon Technologies Ag Halbleiterwafer, Nutzen und elektronisches Bauteil mit gestapelten Halbleiterchips, sowie Verfahren zur Herstellung derselben
JP4204989B2 (ja) * 2004-01-30 2009-01-07 新光電気工業株式会社 半導体装置及びその製造方法
EP1617714B1 (en) 2004-07-16 2008-09-10 STMicroelectronics S.A. Electronic circuit assembly, device comprising such assembly and method for fabricating such device
JP4520355B2 (ja) * 2005-04-19 2010-08-04 パナソニック株式会社 半導体モジュール
US7504283B2 (en) * 2006-12-18 2009-03-17 Texas Instruments Incorporated Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
SG146460A1 (en) * 2007-03-12 2008-10-30 Micron Technology Inc Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components

Also Published As

Publication number Publication date
US8138021B2 (en) 2012-03-20
EP2130224A2 (en) 2009-12-09
US7759785B2 (en) 2010-07-20
US20080224298A1 (en) 2008-09-18
JP2010521818A (ja) 2010-06-24
SG146460A1 (en) 2008-10-30
EP2130224B1 (en) 2019-08-14
KR101407773B1 (ko) 2014-07-02
WO2008112643A2 (en) 2008-09-18
TW200901435A (en) 2009-01-01
CN101632175A (zh) 2010-01-20
CN101632175B (zh) 2012-02-22
KR20090122283A (ko) 2009-11-26
US20100279466A1 (en) 2010-11-04
WO2008112643A3 (en) 2008-12-18
TWI374536B (en) 2012-10-11

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