SG146460A1 - Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components - Google Patents

Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components

Info

Publication number
SG146460A1
SG146460A1 SG200701790-8A SG2007017908A SG146460A1 SG 146460 A1 SG146460 A1 SG 146460A1 SG 2007017908 A SG2007017908 A SG 2007017908A SG 146460 A1 SG146460 A1 SG 146460A1
Authority
SG
Singapore
Prior art keywords
methods
semiconductor devices
packaging
manufacturing
board
Prior art date
Application number
SG200701790-8A
Other languages
English (en)
Inventor
David J Corisis
J Michael Brooks
Lee Choon Kuan
Chong Chin Hui
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to SG200701790-8A priority Critical patent/SG146460A1/en
Priority to US11/742,297 priority patent/US7759785B2/en
Priority to JP2009553715A priority patent/JP5467458B2/ja
Priority to KR1020097021296A priority patent/KR101407773B1/ko
Priority to CN2008800076963A priority patent/CN101632175B/zh
Priority to EP08731831.7A priority patent/EP2130224B1/en
Priority to PCT/US2008/056424 priority patent/WO2008112643A2/en
Priority to TW097108734A priority patent/TWI374536B/zh
Publication of SG146460A1 publication Critical patent/SG146460A1/en
Priority to US12/838,642 priority patent/US8138021B2/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
    • Y10T29/53183—Multilead component

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
SG200701790-8A 2007-03-12 2007-03-12 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components SG146460A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
SG200701790-8A SG146460A1 (en) 2007-03-12 2007-03-12 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
US11/742,297 US7759785B2 (en) 2007-03-12 2007-04-30 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
JP2009553715A JP5467458B2 (ja) 2007-03-12 2008-03-10 半導体デバイス及び部品のパッケージ化装置、半導体デバイス及び部品のパッケージ化方法
KR1020097021296A KR101407773B1 (ko) 2007-03-12 2008-03-10 반도체 장치를 패키징하는 장치, 패지징된 반도체 구성 부품, 반도체 장치를 패키징하는 장치의 제조 방법 및 반도체 구성 부품을 제조하는 방법
CN2008800076963A CN101632175B (zh) 2007-03-12 2008-03-10 用于封装半导体装置的设备和制造半导体组件的方法
EP08731831.7A EP2130224B1 (en) 2007-03-12 2008-03-10 Apparatus for packaging semiconductor devices
PCT/US2008/056424 WO2008112643A2 (en) 2007-03-12 2008-03-10 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
TW097108734A TWI374536B (en) 2007-03-12 2008-03-12 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
US12/838,642 US8138021B2 (en) 2007-03-12 2010-07-19 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200701790-8A SG146460A1 (en) 2007-03-12 2007-03-12 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components

Publications (1)

Publication Number Publication Date
SG146460A1 true SG146460A1 (en) 2008-10-30

Family

ID=39760341

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200701790-8A SG146460A1 (en) 2007-03-12 2007-03-12 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components

Country Status (8)

Country Link
US (2) US7759785B2 (https=)
EP (1) EP2130224B1 (https=)
JP (1) JP5467458B2 (https=)
KR (1) KR101407773B1 (https=)
CN (1) CN101632175B (https=)
SG (1) SG146460A1 (https=)
TW (1) TWI374536B (https=)
WO (1) WO2008112643A2 (https=)

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US8310835B2 (en) * 2009-07-14 2012-11-13 Apple Inc. Systems and methods for providing vias through a modular component
TWI508239B (zh) * 2009-08-20 2015-11-11 精材科技股份有限公司 晶片封裝體及其形成方法
KR101221869B1 (ko) * 2009-08-31 2013-01-15 한국전자통신연구원 반도체 패키지 및 그 제조 방법
CN102237324A (zh) * 2010-04-29 2011-11-09 国碁电子(中山)有限公司 集成电路封装结构及方法
TWI416679B (zh) 2010-12-06 2013-11-21 財團法人工業技術研究院 半導體結構及其製造方法
US8558369B2 (en) * 2011-03-25 2013-10-15 Stats Chippac Ltd. Integrated circuit packaging system with interconnects and method of manufacture thereof
US9281260B2 (en) 2012-03-08 2016-03-08 Infineon Technologies Ag Semiconductor packages and methods of forming the same
CN104067387B (zh) * 2012-03-22 2016-12-14 三菱电机株式会社 半导体装置及其制造方法
US8860202B2 (en) * 2012-08-29 2014-10-14 Macronix International Co., Ltd. Chip stack structure and manufacturing method thereof
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
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US20150221570A1 (en) * 2014-02-04 2015-08-06 Amkor Technology, Inc. Thin sandwich embedded package
US9443744B2 (en) * 2014-07-14 2016-09-13 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
US9515017B2 (en) * 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
US9230900B1 (en) * 2014-12-18 2016-01-05 Intel Corporation Ground via clustering for crosstalk mitigation
US9397078B1 (en) * 2015-03-02 2016-07-19 Micron Technology, Inc. Semiconductor device assembly with underfill containment cavity
CN105390477B (zh) * 2015-12-11 2018-08-17 苏州捷研芯纳米科技有限公司 一种多芯片3d二次封装半导体器件及其封装方法
US10388636B2 (en) 2015-12-21 2019-08-20 Intel Corporation Integrating system in package (SIP) with input/output (IO) board for platform miniaturization
CN106098676A (zh) * 2016-08-15 2016-11-09 黄卫东 多通道堆叠封装结构及封装方法
US10229859B2 (en) * 2016-08-17 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
KR102647213B1 (ko) 2016-12-31 2024-03-15 인텔 코포레이션 전자 디바이스 패키지
US10319684B2 (en) * 2017-04-11 2019-06-11 STATS ChipPAC Pte. Ltd. Dummy conductive structures for EMI shielding
JP7003439B2 (ja) * 2017-04-27 2022-01-20 富士電機株式会社 半導体装置
US10403602B2 (en) 2017-06-29 2019-09-03 Intel IP Corporation Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory
US10529592B2 (en) * 2017-12-04 2020-01-07 Micron Technology, Inc. Semiconductor device assembly with pillar array
US11257803B2 (en) * 2018-08-25 2022-02-22 Octavo Systems Llc System in a package connectors
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Also Published As

Publication number Publication date
US8138021B2 (en) 2012-03-20
EP2130224A2 (en) 2009-12-09
US7759785B2 (en) 2010-07-20
US20080224298A1 (en) 2008-09-18
JP2010521818A (ja) 2010-06-24
EP2130224B1 (en) 2019-08-14
KR101407773B1 (ko) 2014-07-02
WO2008112643A2 (en) 2008-09-18
TW200901435A (en) 2009-01-01
CN101632175A (zh) 2010-01-20
CN101632175B (zh) 2012-02-22
KR20090122283A (ko) 2009-11-26
US20100279466A1 (en) 2010-11-04
WO2008112643A3 (en) 2008-12-18
JP5467458B2 (ja) 2014-04-09
TWI374536B (en) 2012-10-11

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