JP5459959B2 - マルチチップ・ウェハレベル・パッケージを形成する方法 - Google Patents

マルチチップ・ウェハレベル・パッケージを形成する方法 Download PDF

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Publication number
JP5459959B2
JP5459959B2 JP2007541952A JP2007541952A JP5459959B2 JP 5459959 B2 JP5459959 B2 JP 5459959B2 JP 2007541952 A JP2007541952 A JP 2007541952A JP 2007541952 A JP2007541952 A JP 2007541952A JP 5459959 B2 JP5459959 B2 JP 5459959B2
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Japan
Prior art keywords
chip
chips
wafer
forming
carrier substrate
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Expired - Fee Related
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JP2007541952A
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Japanese (ja)
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JP2008521228A5 (https=
JP2008521228A (ja
Inventor
バレル、ロイド
チェン、ハワード、ハオ
シュー、ルイス
ソーター、ウルフガング
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H10P72/7414—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support the auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates

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  • Semiconductor Integrated Circuits (AREA)
  • Dicing (AREA)
  • Wire Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2007541952A 2004-11-20 2005-11-16 マルチチップ・ウェハレベル・パッケージを形成する方法 Expired - Fee Related JP5459959B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/994,494 2004-11-20
US10/994,494 US7405108B2 (en) 2004-11-20 2004-11-20 Methods for forming co-planar wafer-scale chip packages
PCT/EP2005/056009 WO2006053879A1 (en) 2004-11-20 2005-11-16 Methods for forming co-planar wafer-scale chip packages

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011160519A Division JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Publications (3)

Publication Number Publication Date
JP2008521228A JP2008521228A (ja) 2008-06-19
JP2008521228A5 JP2008521228A5 (https=) 2008-10-02
JP5459959B2 true JP5459959B2 (ja) 2014-04-02

Family

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Family Applications (2)

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JP2007541952A Expired - Fee Related JP5459959B2 (ja) 2004-11-20 2005-11-16 マルチチップ・ウェハレベル・パッケージを形成する方法
JP2011160519A Expired - Fee Related JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Family Applications After (1)

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JP2011160519A Expired - Fee Related JP5474002B2 (ja) 2004-11-20 2011-07-22 マルチチップ・ウェハレベル・パッケージを形成する方法

Country Status (9)

Country Link
US (2) US7405108B2 (https=)
EP (1) EP1817793B1 (https=)
JP (2) JP5459959B2 (https=)
KR (1) KR100992015B1 (https=)
CN (1) CN100437952C (https=)
AT (1) ATE477588T1 (https=)
DE (1) DE602005022919D1 (https=)
TW (1) TWI362706B (https=)
WO (1) WO2006053879A1 (https=)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages
US7442579B2 (en) * 2004-11-22 2008-10-28 International Business Machines Corporation Methods to achieve precision alignment for wafer scale packages
DE102005039479B3 (de) * 2005-08-18 2007-03-29 Infineon Technologies Ag Halbleiterbauteil mit gedünntem Halbleiterchip und Verfahren zur Herstellung des gedünnten Halbleiterbauteils
US7658901B2 (en) * 2005-10-14 2010-02-09 The Trustees Of Princeton University Thermally exfoliated graphite oxide
JP4559993B2 (ja) * 2006-03-29 2010-10-13 株式会社東芝 半導体装置の製造方法
KR100829392B1 (ko) * 2006-08-24 2008-05-13 동부일렉트로닉스 주식회사 ＳｏＣ 및 그 제조 방법
TW200941661A (en) * 2008-03-19 2009-10-01 Integrated Circuit Solution Inc Shape of window formed in a substrate for window ball grid array package
JP4828559B2 (ja) * 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
US8772087B2 (en) * 2009-10-22 2014-07-08 Infineon Technologies Ag Method and apparatus for semiconductor device fabrication using a reconstituted wafer
US8322022B1 (en) 2010-06-28 2012-12-04 Western Digital (Fremont), Llc Method for providing an energy assisted magnetic recording head in a wafer packaging configuration
CN102386088B (zh) * 2010-09-03 2014-06-25 中芯国际集成电路制造(上海)有限公司 用于去除半导体器件结构上的光致抗蚀剂层的方法
CN102769002B (zh) * 2011-04-30 2016-09-14 中国科学院微电子研究所 半导体器件及其形成方法、封装结构
JP6063641B2 (ja) * 2012-05-16 2017-01-18 株式会社ディスコ ウエーハ保護部材
WO2015043495A1 (zh) * 2013-09-30 2015-04-02 南通富士通微电子股份有限公司 晶圆封装结构和封装方法
US9123546B2 (en) 2013-11-14 2015-09-01 Taiwan Semiconductor Manufacturing Company Limited Multi-layer semiconductor device structures with different channel materials
US9350339B2 (en) 2014-07-18 2016-05-24 Qualcomm Incorporated Systems and methods for clock distribution in a die-to-die interface
JP6341959B2 (ja) 2016-05-27 2018-06-13 浜松ホトニクス株式会社 ファブリペロー干渉フィルタの製造方法
US11041755B2 (en) 2016-05-27 2021-06-22 Hamamatsu Photonics K.K. Production method for Fabry-Perot interference filter
FI3505987T3 (fi) 2016-08-24 2023-12-19 Hamamatsu Photonics Kk Fabry-perot-häiriösuodatin
US10916507B2 (en) 2018-12-04 2021-02-09 International Business Machines Corporation Multiple chip carrier for bridge assembly
GB2582384B (en) * 2019-03-22 2023-10-18 Cirrus Logic Int Semiconductor Ltd Semiconductor structures
US11456247B2 (en) * 2019-06-13 2022-09-27 Nanya Technology Corporation Semiconductor device and fabrication method for the same
CN110690868B (zh) * 2019-09-27 2021-02-19 无锡市好达电子股份有限公司 一种滤波器的新型晶圆级封装方法
CN111128716B (zh) * 2019-11-15 2023-10-17 西安电子科技大学 一种大面积图形自对准的异质集成方法
KR102766434B1 (ko) 2020-03-26 2025-02-12 삼성전자주식회사 반도체 스택 및 그 제조 방법
US11545404B2 (en) * 2020-05-06 2023-01-03 Qualcomm Incorporated III-V compound semiconductor dies with stress-treated inactive surfaces to avoid packaging-induced fractures, and related methods
TWI790003B (zh) * 2021-11-18 2023-01-11 佳邦科技股份有限公司 過電壓保護元件

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281745A (ja) 1985-10-05 1987-04-15 Fujitsu Ltd ウエハ−規模のｌｓｉ半導体装置とその製造方法
US4866501A (en) * 1985-12-16 1989-09-12 American Telephone And Telegraph Company At&T Bell Laboratories Wafer scale integration
US5091331A (en) 1990-04-16 1992-02-25 Harris Corporation Ultra-thin circuit fabrication by controlled wafer debonding
JPH0645436A (ja) * 1992-07-22 1994-02-18 Nec Corp 半導体基板の貼付方法
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
JPH0878487A (ja) * 1994-08-31 1996-03-22 Nec Kyushu Ltd 半導体基板および半導体装置の製造方法
US5770884A (en) * 1995-06-30 1998-06-23 International Business Machines Corporation Very dense integrated circuit package
US5880007A (en) * 1997-09-30 1999-03-09 Siemens Aktiengesellschaft Planarization of a non-conformal device layer in semiconductor fabrication
US6177299B1 (en) * 1998-01-15 2001-01-23 International Business Machines Corporation Transistor having substantially isolated body and method of making the same
JPH11354667A (ja) * 1998-06-05 1999-12-24 Nippon Telegr & Teleph Corp <Ntt> 電子部品およびその実装方法
US6627477B1 (en) * 2000-09-07 2003-09-30 International Business Machines Corporation Method of assembling a plurality of semiconductor devices having different thickness
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
JP2003197850A (ja) * 2001-12-26 2003-07-11 Sony Corp 半導体装置及びその製造方法
JP4260405B2 (ja) * 2002-02-08 2009-04-30 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US7203393B2 (en) * 2002-03-08 2007-04-10 Movaz Networks, Inc. MEMS micro mirrors driven by electrodes fabricated on another substrate
WO2003100829A2 (en) * 2002-05-20 2003-12-04 Imagerlabs Forming a multi segment integrated circuit with isolated substrates
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
US7078320B2 (en) * 2004-08-10 2006-07-18 International Business Machines Corporation Partial wafer bonding and dicing
US7005319B1 (en) * 2004-11-19 2006-02-28 International Business Machines Corporation Global planarization of wafer scale package with precision die thickness control
US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages

Also Published As

Publication number Publication date
EP1817793B1 (en) 2010-08-11
JP5474002B2 (ja) 2014-04-16
KR20070085402A (ko) 2007-08-27
US7405108B2 (en) 2008-07-29
WO2006053879A1 (en) 2006-05-26
US7867820B2 (en) 2011-01-11
US20080280399A1 (en) 2008-11-13
CN100437952C (zh) 2008-11-26
US20060110851A1 (en) 2006-05-25
TW200633081A (en) 2006-09-16
EP1817793A1 (en) 2007-08-15
JP2011249830A (ja) 2011-12-08
DE602005022919D1 (de) 2010-09-23
JP2008521228A (ja) 2008-06-19
TWI362706B (en) 2012-04-21
CN101027765A (zh) 2007-08-29
ATE477588T1 (de) 2010-08-15
KR100992015B1 (ko) 2010-11-05

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