JP5409801B2 - 有機表面パッシベーションでめっきの進行に差を付けて遅らせることによるボトムアップめっき - Google Patents

有機表面パッシベーションでめっきの進行に差を付けて遅らせることによるボトムアップめっき Download PDF

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Publication number
JP5409801B2
JP5409801B2 JP2011537626A JP2011537626A JP5409801B2 JP 5409801 B2 JP5409801 B2 JP 5409801B2 JP 2011537626 A JP2011537626 A JP 2011537626A JP 2011537626 A JP2011537626 A JP 2011537626A JP 5409801 B2 JP5409801 B2 JP 5409801B2
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Japan
Prior art keywords
passivation film
substrate
trench
seed layer
via structure
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP2011537626A
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Japanese (ja)
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JP2012510162A5 (https=
JP2012510162A (ja
Inventor
ジェン−ユエ ワン，
ファー チャン，
ロン タオ，
ホン チャン，
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Applied Materials Inc
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Applied Materials Inc
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Publication of JP2012510162A5 publication Critical patent/JP2012510162A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemically Coating (AREA)
JP2011537626A 2008-11-24 2009-11-19 有機表面パッシベーションでめっきの進行に差を付けて遅らせることによるボトムアップめっき Expired - Fee Related JP5409801B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11754008P 2008-11-24 2008-11-24
US61/117,540 2008-11-24
US12/620,818 US8293647B2 (en) 2008-11-24 2009-11-18 Bottom up plating by organic surface passivation and differential plating retardation
US12/620,818 2009-11-18
PCT/US2009/065193 WO2010059857A2 (en) 2008-11-24 2009-11-19 Bottom up plating by organic surface passivation and differential plating retardation

Publications (3)

Publication Number Publication Date
JP2012510162A JP2012510162A (ja) 2012-04-26
JP2012510162A5 JP2012510162A5 (https=) 2013-01-17
JP5409801B2 true JP5409801B2 (ja) 2014-02-05

Family

ID=42196702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011537626A Expired - Fee Related JP5409801B2 (ja) 2008-11-24 2009-11-19 有機表面パッシベーションでめっきの進行に差を付けて遅らせることによるボトムアップめっき

Country Status (6)

Country Link
US (1) US8293647B2 (https=)
JP (1) JP5409801B2 (https=)
KR (1) KR101368308B1 (https=)
CN (1) CN102224574B (https=)
TW (1) TWI397616B (https=)
WO (1) WO2010059857A2 (https=)

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JP5667485B2 (ja) * 2011-03-17 2015-02-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法、及び半導体装置
US20130051530A1 (en) * 2011-08-30 2013-02-28 Fujifilm Corporation High Aspect Ratio Grid for Phase Contrast X-ray Imaging and Method of Making the Same
CN102798471B (zh) * 2011-10-19 2015-08-12 清华大学 一种红外探测器及其制备方法
US8754531B2 (en) * 2012-03-14 2014-06-17 Nanya Technology Corp. Through-silicon via with a non-continuous dielectric layer
CN113862634A (zh) 2012-03-27 2021-12-31 诺发系统公司 钨特征填充
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR101972969B1 (ko) * 2012-08-20 2019-04-29 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
CN104112697B (zh) * 2013-04-18 2017-09-15 中芯国际集成电路制造(上海)有限公司 一种改善铜填充质量的方法
JP6187008B2 (ja) * 2013-08-07 2017-08-30 大日本印刷株式会社 金属充填構造体の製造方法及び金属充填構造体
US9899234B2 (en) 2014-06-30 2018-02-20 Lam Research Corporation Liner and barrier applications for subtractive metal integration
US9349637B2 (en) * 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9859124B2 (en) * 2015-04-17 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd Method of manufacturing semiconductor device with recess
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US20160351493A1 (en) * 2015-05-27 2016-12-01 Macronix International Co., Ltd. Semiconductor device and manufacturing method for the same
JP7125343B2 (ja) * 2015-10-23 2022-08-24 アプライド マテリアルズ インコーポレイテッド 表面毒化処理によるボトムアップ式間隙充填
US10438847B2 (en) 2016-05-13 2019-10-08 Lam Research Corporation Manganese barrier and adhesion layers for cobalt
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
US10242879B2 (en) 2017-04-20 2019-03-26 Lam Research Corporation Methods and apparatus for forming smooth and conformal cobalt film by atomic layer deposition
WO2020118100A1 (en) 2018-12-05 2020-06-11 Lam Research Corporation Void free low stress fill
SG11202108725XA (en) 2019-02-13 2021-09-29 Lam Res Corp Tungsten feature fill with inhibition control
US11781215B2 (en) * 2019-06-18 2023-10-10 Tokyo Electron Limited Substrate processing method of forming a plating film in a recess

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Also Published As

Publication number Publication date
TWI397616B (zh) 2013-06-01
WO2010059857A3 (en) 2010-08-19
JP2012510162A (ja) 2012-04-26
CN102224574B (zh) 2014-06-11
US8293647B2 (en) 2012-10-23
KR20110102374A (ko) 2011-09-16
TW201026911A (en) 2010-07-16
CN102224574A (zh) 2011-10-19
KR101368308B1 (ko) 2014-02-26
US20100130007A1 (en) 2010-05-27
WO2010059857A2 (en) 2010-05-27

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