CN102224574B - 利用有机表面钝化及微差电镀延迟进行由底部往上镀层的方法 - Google Patents

利用有机表面钝化及微差电镀延迟进行由底部往上镀层的方法 Download PDF

Info

Publication number
CN102224574B
CN102224574B CN200980147108.0A CN200980147108A CN102224574B CN 102224574 B CN102224574 B CN 102224574B CN 200980147108 A CN200980147108 A CN 200980147108A CN 102224574 B CN102224574 B CN 102224574B
Authority
CN
China
Prior art keywords
trench
via structure
passivation film
seed layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200980147108.0A
Other languages
English (en)
Chinese (zh)
Other versions
CN102224574A (zh
Inventor
王建乐
钟华
陶荣
张宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN102224574A publication Critical patent/CN102224574A/zh
Application granted granted Critical
Publication of CN102224574B publication Critical patent/CN102224574B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemically Coating (AREA)
CN200980147108.0A 2008-11-24 2009-11-19 利用有机表面钝化及微差电镀延迟进行由底部往上镀层的方法 Expired - Fee Related CN102224574B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11754008P 2008-11-24 2008-11-24
US61/117,540 2008-11-24
US12/620,818 US8293647B2 (en) 2008-11-24 2009-11-18 Bottom up plating by organic surface passivation and differential plating retardation
US12/620,818 2009-11-18
PCT/US2009/065193 WO2010059857A2 (en) 2008-11-24 2009-11-19 Bottom up plating by organic surface passivation and differential plating retardation

Publications (2)

Publication Number Publication Date
CN102224574A CN102224574A (zh) 2011-10-19
CN102224574B true CN102224574B (zh) 2014-06-11

Family

ID=42196702

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200980147108.0A Expired - Fee Related CN102224574B (zh) 2008-11-24 2009-11-19 利用有机表面钝化及微差电镀延迟进行由底部往上镀层的方法

Country Status (6)

Country Link
US (1) US8293647B2 (https=)
JP (1) JP5409801B2 (https=)
KR (1) KR101368308B1 (https=)
CN (1) CN102224574B (https=)
TW (1) TWI397616B (https=)
WO (1) WO2010059857A2 (https=)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
JP5667485B2 (ja) * 2011-03-17 2015-02-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法、及び半導体装置
US20130051530A1 (en) * 2011-08-30 2013-02-28 Fujifilm Corporation High Aspect Ratio Grid for Phase Contrast X-ray Imaging and Method of Making the Same
CN102798471B (zh) * 2011-10-19 2015-08-12 清华大学 一种红外探测器及其制备方法
US8754531B2 (en) * 2012-03-14 2014-06-17 Nanya Technology Corp. Through-silicon via with a non-continuous dielectric layer
CN113862634A (zh) 2012-03-27 2021-12-31 诺发系统公司 钨特征填充
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR101972969B1 (ko) * 2012-08-20 2019-04-29 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
CN104112697B (zh) * 2013-04-18 2017-09-15 中芯国际集成电路制造(上海)有限公司 一种改善铜填充质量的方法
JP6187008B2 (ja) * 2013-08-07 2017-08-30 大日本印刷株式会社 金属充填構造体の製造方法及び金属充填構造体
US9899234B2 (en) 2014-06-30 2018-02-20 Lam Research Corporation Liner and barrier applications for subtractive metal integration
US9349637B2 (en) * 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9859124B2 (en) * 2015-04-17 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd Method of manufacturing semiconductor device with recess
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US20160351493A1 (en) * 2015-05-27 2016-12-01 Macronix International Co., Ltd. Semiconductor device and manufacturing method for the same
JP7125343B2 (ja) * 2015-10-23 2022-08-24 アプライド マテリアルズ インコーポレイテッド 表面毒化処理によるボトムアップ式間隙充填
US10438847B2 (en) 2016-05-13 2019-10-08 Lam Research Corporation Manganese barrier and adhesion layers for cobalt
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
US10242879B2 (en) 2017-04-20 2019-03-26 Lam Research Corporation Methods and apparatus for forming smooth and conformal cobalt film by atomic layer deposition
WO2020118100A1 (en) 2018-12-05 2020-06-11 Lam Research Corporation Void free low stress fill
SG11202108725XA (en) 2019-02-13 2021-09-29 Lam Res Corp Tungsten feature fill with inhibition control
US11781215B2 (en) * 2019-06-18 2023-10-10 Tokyo Electron Limited Substrate processing method of forming a plating film in a recess

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010004718A (ko) * 1999-06-29 2001-01-15 김영환 반도체 소자의 금속 배선 형성 방법
KR20050011105A (ko) * 2003-07-21 2005-01-29 매그나칩 반도체 유한회사 반도체 소자의 ｒｆ 인덕터 제조 방법
KR20060078112A (ko) * 2004-12-30 2006-07-05 삼성전기주식회사 내부 비아홀의 필 도금 구조 및 그 제조 방법

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959874A (en) * 1974-12-20 1976-06-01 Western Electric Company, Inc. Method of forming an integrated circuit assembly
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
US6410418B1 (en) * 1999-08-18 2002-06-25 Advanced Micro Devices, Inc. Recess metallization via selective insulator formation on nucleation/seed layer
KR100331570B1 (ko) * 2000-06-13 2002-04-06 윤종용 전기도금법을 이용한 반도체 메모리 소자의 커패시터제조방법
US6787460B2 (en) * 2002-01-14 2004-09-07 Samsung Electronics Co., Ltd. Methods of forming metal layers in integrated circuit devices using selective deposition on edges of recesses and conductive contacts so formed
KR100465063B1 (ko) * 2002-04-01 2005-01-06 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법
US7628897B2 (en) * 2002-10-23 2009-12-08 Applied Materials, Inc. Reactive ion etching for semiconductor device feature topography modification
US20040248375A1 (en) * 2003-06-04 2004-12-09 Mcneil John Trench filling methods
KR100599434B1 (ko) * 2003-10-20 2006-07-14 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법
KR20050056383A (ko) 2003-12-10 2005-06-16 매그나칩 반도체 유한회사 반도체 소자의 금속배선 형성방법
US7068138B2 (en) * 2004-01-29 2006-06-27 International Business Machines Corporation High Q factor integrated circuit inductor
CN100565815C (zh) * 2004-10-08 2009-12-02 西尔弗布鲁克研究有限公司 从蚀刻沟槽中移除聚合物涂层的方法
JP2006274369A (ja) 2005-03-29 2006-10-12 Ebara Corp 基板配線形成方法、基板配線形成装置、及びめっき抑制物質転写スタンプ
JP2007009247A (ja) * 2005-06-28 2007-01-18 Ebara Corp 基板処理装置及び基板処理方法
JP2007149824A (ja) * 2005-11-25 2007-06-14 Ebara Corp 成膜方法及び成膜装置
US7709320B2 (en) * 2006-06-28 2010-05-04 International Business Machines Corporation Method of fabricating trench capacitors and memory cells using trench capacitors
US20080124924A1 (en) * 2006-07-18 2008-05-29 Applied Materials, Inc. Scheme for copper filling in vias and trenches
US20080026555A1 (en) * 2006-07-26 2008-01-31 Dubin Valery M Sacrificial tapered trench opening for damascene interconnects
US7560222B2 (en) * 2006-10-31 2009-07-14 International Business Machines Corporation Si-containing polymers for nano-pattern device fabrication
US7915115B2 (en) * 2008-06-03 2011-03-29 International Business Machines Corporation Method for forming dual high-k metal gate using photoresist mask and structures thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010004718A (ko) * 1999-06-29 2001-01-15 김영환 반도체 소자의 금속 배선 형성 방법
KR20050011105A (ko) * 2003-07-21 2005-01-29 매그나칩 반도체 유한회사 반도체 소자의 ｒｆ 인덕터 제조 방법
KR20060078112A (ko) * 2004-12-30 2006-07-05 삼성전기주식회사 내부 비아홀의 필 도금 구조 및 그 제조 방법

Also Published As

Publication number Publication date
JP5409801B2 (ja) 2014-02-05
TWI397616B (zh) 2013-06-01
WO2010059857A3 (en) 2010-08-19
JP2012510162A (ja) 2012-04-26
US8293647B2 (en) 2012-10-23
KR20110102374A (ko) 2011-09-16
TW201026911A (en) 2010-07-16
CN102224574A (zh) 2011-10-19
KR101368308B1 (ko) 2014-02-26
US20100130007A1 (en) 2010-05-27
WO2010059857A2 (en) 2010-05-27

Similar Documents

Publication Publication Date Title
CN102224574B (zh) 利用有机表面钝化及微差电镀延迟进行由底部往上镀层的方法
US20060189127A1 (en) Method to improve palanarity of electroplated copper
KR102546486B1 (ko) 도금 처리 방법, 도금 처리 장치 및 기억 매체
JP5446126B2 (ja) 電解メッキ方法および半導体装置の製造方法
JP2012510162A5 (https=)
US6784105B1 (en) Simultaneous native oxide removal and metal neutral deposition method
JP4408432B2 (ja) ダマシン配線の形成方法
KR100887444B1 (ko) 플라즈마 스퍼터링에 의한 성막방법 및 성막장치
CN107858728B (zh) Tsv电镀方法
CN105280614A (zh) 用于在反应性金属膜上电化学沉积金属的方法
CN100546014C (zh) 沉积金属、形成金属化层和改善cmp过程的均匀性的方法
JP4127359B2 (ja) 集積回路デバイスの製造方法
Yin et al. Effect of sputtering process parameters on the uniformity of copper film deposited in micro-via
JP2006019708A (ja) 半導体装置の製造方法及び半導体装置
US8445376B2 (en) Post-etching treatment process for copper interconnecting wires
CN107895710A (zh) 导通孔的铜填充工艺
CN106057727B (zh) 制造具有凹槽的半导体器件的方法
Xiong et al. Investigation of bottom-up electrodeposition filling for nanoscale through-silicon vias (TSVs)
US20070134929A1 (en) Etching method and etching apparatus
CN113026067A (zh) 晶圆级封装的电镀溶液及电镀工艺
KR20200080122A (ko) 반도체 소자의 제조 방법
JP2006515467A (ja) 後続の化学機械研磨（ＣＭＰ：ＣｈｅｍｉｃａｌＭｅｃｈａｎｉｃａｌＰｏｌｉｓｈｉｎｇ）プロセスのプロセス均一性が向上するようにパターン誘電層上に銅を電気メッキするための方法
JP2007084891A (ja) 配線基板のメッキ膜形成方法
JP2005340830A (ja) コンタクトホール内の金属窒化膜の形成方法、及びその方法によって形成された金属窒化膜
HK40080366A (en) Coating method, chip substrate and chip

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Address after: California, USA

Applicant after: APPLIED MATERIALS, Inc.

Address before: California, USA

Applicant before: APPLIED MATERIALS, Inc.

SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140611

Termination date: 20201119