JP2012510162A - 有機表面パッシベーションでめっきの進行に差を付けて遅らせることによるボトムアップめっき - Google Patents
有機表面パッシベーションでめっきの進行に差を付けて遅らせることによるボトムアップめっき Download PDFInfo
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- JP2012510162A JP2012510162A JP2011537626A JP2011537626A JP2012510162A JP 2012510162 A JP2012510162 A JP 2012510162A JP 2011537626 A JP2011537626 A JP 2011537626A JP 2011537626 A JP2011537626 A JP 2011537626A JP 2012510162 A JP2012510162 A JP 2012510162A
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- Prior art keywords
- substrate
- seed layer
- passivation film
- trench
- via structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
- H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric
Abstract
Description
Claims (15)
- 基板を処理する方法であって、
トレンチ構造又はビア構造が形成された基板を覆うようにシード層を形成することと、
前記シード層の一部を有機パッシベーション膜で被覆することと、
前記トレンチ構造又はビア構造をめっき液に浸漬して、前記有機パッシベーション膜で被覆されないシード層部分の上に導電材料を堆積させることと
を含む方法。 - 前記シード層の一部を被覆することが、前記トレンチ構造又はビア構造の上部を覆うシード層を被覆することを含む、請求項1に記載の方法。
- 前記有機パッシベーション膜は、前記めっき液に溶解させることができる、請求項2に記載の方法。
- 前記シード層の一部を被覆することが、有機界面活性剤を含有する溶液を前記基板上にスピン塗布することを含む、請求項3に記載の方法。
- 前記シード層の一部を被覆することが、更に、前記トレンチ構造又はビア構造内への有機パッシベーション膜の目標深さに応じてスピン塗布の回転速度を決定することを含む、請求項4に記載の方法。
- 前記有機界面活性剤が1−2−3−ベンゾトリアゾール(BTA)を含む、請求項4に記載の方法。
- 前記溶液がイソプロピルアルコール(IPA)を含む、請求項6に記載の方法。
- 前記シード層の一部を被覆することが、有機界面活性剤を含有する溶液に前記基板を浸漬することを含む、請求項3に記載の方法。
- 前記溶液が、
疎水性担体と、
疎水性担体に懸濁された前記有機界面活性剤と
を含む、請求項8に記載の方法。 - 前記基板を前記めっき液から取り出すことと、
前記シード層の、これまで前記パッシベーション膜で被覆されていた部分から前記パッシベーション膜を除去することと、
前記基板を前記めっき液に浸漬して、前記基板に前記導電材料をめっきすることと
を更に含む、請求項2に記載の方法。 - 前記パッシベーション膜を除去することが、前記基板をアニールすることを含む、請求項10に記載の方法。
- 基板を処理する方法であって、
トレンチ構造又はビア構造が形成された基板を覆うようにシード層を堆積させることと、
前記基板にスピン塗布して、前記シード層の少なくとも一部を覆うようにパッシベーション膜を形成することと、
前記トレンチ構造又はビア構造をめっき液に浸漬して、前記パッシベーション膜で被覆されないシード層部分の上に導電材料を堆積させ、前記パッシベーション膜を前記めっき液に溶解させることと
を含む方法。 - 前記基板にスピン塗布することが、前記パッシベーション膜が前記トレンチ構造又はビア構造の側壁に沿って達する深さを制御することを含む、請求項12に記載の方法。
- 深さを制御することが、
スピン回転速度を上げて前記深さを小さくすることと、
前記スピン回転速度を下げて前記深さを深くすることと
を含む、請求項13に記載の方法。 - 深さを制御することが、更に、スピン塗布中に異なる粘度の担体を使用して前記深さを小さくすることを含む、請求項14に記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11754008P | 2008-11-24 | 2008-11-24 | |
US61/117,540 | 2008-11-24 | ||
US12/620,818 | 2009-11-18 | ||
US12/620,818 US8293647B2 (en) | 2008-11-24 | 2009-11-18 | Bottom up plating by organic surface passivation and differential plating retardation |
PCT/US2009/065193 WO2010059857A2 (en) | 2008-11-24 | 2009-11-19 | Bottom up plating by organic surface passivation and differential plating retardation |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012510162A true JP2012510162A (ja) | 2012-04-26 |
JP2012510162A5 JP2012510162A5 (ja) | 2013-01-17 |
JP5409801B2 JP5409801B2 (ja) | 2014-02-05 |
Family
ID=42196702
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011537626A Expired - Fee Related JP5409801B2 (ja) | 2008-11-24 | 2009-11-19 | 有機表面パッシベーションでめっきの進行に差を付けて遅らせることによるボトムアップめっき |
Country Status (6)
Country | Link |
---|---|
US (1) | US8293647B2 (ja) |
JP (1) | JP5409801B2 (ja) |
KR (1) | KR101368308B1 (ja) |
CN (1) | CN102224574B (ja) |
TW (1) | TWI397616B (ja) |
WO (1) | WO2010059857A2 (ja) |
Cited By (4)
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JP2012195488A (ja) * | 2011-03-17 | 2012-10-11 | Renesas Electronics Corp | 半導体装置の製造方法、及び半導体装置 |
JP2015034306A (ja) * | 2013-08-07 | 2015-02-19 | 大日本印刷株式会社 | 金属充填構造体の製造方法及び金属充填構造体 |
JP2018533218A (ja) * | 2015-10-23 | 2018-11-08 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | 表面毒化処理によるボトムアップ式間隙充填 |
JPWO2020255772A1 (ja) * | 2019-06-18 | 2020-12-24 |
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US10256142B2 (en) | 2009-08-04 | 2019-04-09 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
US20130051530A1 (en) * | 2011-08-30 | 2013-02-28 | Fujifilm Corporation | High Aspect Ratio Grid for Phase Contrast X-ray Imaging and Method of Making the Same |
CN102798471B (zh) * | 2011-10-19 | 2015-08-12 | 清华大学 | 一种红外探测器及其制备方法 |
US8754531B2 (en) * | 2012-03-14 | 2014-06-17 | Nanya Technology Corp. | Through-silicon via with a non-continuous dielectric layer |
US11437269B2 (en) | 2012-03-27 | 2022-09-06 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
KR102064627B1 (ko) | 2012-03-27 | 2020-01-09 | 노벨러스 시스템즈, 인코포레이티드 | 텅스텐 피처 충진 |
US10381266B2 (en) | 2012-03-27 | 2019-08-13 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
KR101972969B1 (ko) * | 2012-08-20 | 2019-04-29 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
CN104112697B (zh) * | 2013-04-18 | 2017-09-15 | 中芯国际集成电路制造(上海)有限公司 | 一种改善铜填充质量的方法 |
US9899234B2 (en) | 2014-06-30 | 2018-02-20 | Lam Research Corporation | Liner and barrier applications for subtractive metal integration |
US9349637B2 (en) * | 2014-08-21 | 2016-05-24 | Lam Research Corporation | Method for void-free cobalt gap fill |
US9997405B2 (en) | 2014-09-30 | 2018-06-12 | Lam Research Corporation | Feature fill with nucleation inhibition |
US9859124B2 (en) * | 2015-04-17 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company Ltd | Method of manufacturing semiconductor device with recess |
US10170320B2 (en) | 2015-05-18 | 2019-01-01 | Lam Research Corporation | Feature fill with multi-stage nucleation inhibition |
US20160351493A1 (en) * | 2015-05-27 | 2016-12-01 | Macronix International Co., Ltd. | Semiconductor device and manufacturing method for the same |
US10438847B2 (en) | 2016-05-13 | 2019-10-08 | Lam Research Corporation | Manganese barrier and adhesion layers for cobalt |
US10573522B2 (en) | 2016-08-16 | 2020-02-25 | Lam Research Corporation | Method for preventing line bending during metal fill process |
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- 2009-11-19 WO PCT/US2009/065193 patent/WO2010059857A2/en active Application Filing
- 2009-11-19 JP JP2011537626A patent/JP5409801B2/ja not_active Expired - Fee Related
- 2009-11-19 TW TW098139365A patent/TWI397616B/zh not_active IP Right Cessation
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012195488A (ja) * | 2011-03-17 | 2012-10-11 | Renesas Electronics Corp | 半導体装置の製造方法、及び半導体装置 |
JP2015034306A (ja) * | 2013-08-07 | 2015-02-19 | 大日本印刷株式会社 | 金属充填構造体の製造方法及び金属充填構造体 |
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Also Published As
Publication number | Publication date |
---|---|
US8293647B2 (en) | 2012-10-23 |
TWI397616B (zh) | 2013-06-01 |
CN102224574B (zh) | 2014-06-11 |
KR101368308B1 (ko) | 2014-02-26 |
US20100130007A1 (en) | 2010-05-27 |
WO2010059857A3 (en) | 2010-08-19 |
JP5409801B2 (ja) | 2014-02-05 |
KR20110102374A (ko) | 2011-09-16 |
WO2010059857A2 (en) | 2010-05-27 |
CN102224574A (zh) | 2011-10-19 |
TW201026911A (en) | 2010-07-16 |
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