TWI443224B - 藉由包含無電和供電的階段之溼式化學沉積而於圖案化之電介質之上形成金屬層之方法 - Google Patents
藉由包含無電和供電的階段之溼式化學沉積而於圖案化之電介質之上形成金屬層之方法 Download PDFInfo
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- TWI443224B TWI443224B TW095148704A TW95148704A TWI443224B TW I443224 B TWI443224 B TW I443224B TW 095148704 A TW095148704 A TW 095148704A TW 95148704 A TW95148704 A TW 95148704A TW I443224 B TWI443224 B TW I443224B
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- Prior art keywords
- layer
- barrier layer
- deposition
- metal
- wet chemical
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Classifications
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/18—Electroplating using modulated, pulsed or reversing current
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- C—CHEMISTRY; METALLURGY
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
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- C25D5/60—Electroplating characterised by the structure or texture of the layers
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
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- H01—ELECTRIC ELEMENTS
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/76855—After-treatment introducing at least one additional element into the layer
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- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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Description
本發明大體上係關於製造積體電路之領域,且尤係關於在包含溝槽和通孔之圖案化電介質材料之上,用濕式化學沉積製程形成金屬層。
於積體電路中,大量之電路元件,譬如電晶體、電容器、電阻器等形成在適當的基板內或基板上,通常以大致的平面構形。由於大量之電路元件和所需複雜之用於先進應用之積體電路佈局,個別電路元件之電性連接一般不建構在所製造電路元件之相同的層級(level)中,但需要一個或多個額外的“接線”層,亦稱之為金屬化層。這些金屬化層通常包括提供層內(inner-level)電性連接之金屬線,並亦包括稱之為通孔(via)之複數個層間連接(inter-level connection),其中該等金屬線和通孔亦可共同稱之為互連(interconnect)。
由於在現代積體電路中持續縮小電路元件之特徵(feature)尺寸,因此對於指定晶片面積之電路元件之數目(亦即裝填密度(packing density))亦增加,因而甚至需要更增多的電性互連數目,以提供所希望之電路功能。因此,當對於每晶片面積之電路元件之數目變得較大時,堆疊之金屬化層之數目可增加。因為製造複數個金屬化層需要解決極富挑戰性的問題,例如像是用於複雜之微處理器基礎之複數個堆疊金屬層之機械、熱和電可靠性,因此半導體製造者愈益藉由允許較高電流密度之金屬來替代已熟知的金屬化金屬鋁,並因此允許減少互連之尺寸。舉例來說,銅為一般考慮用來取代鋁之可執行之候選金屬,這是因為當他們與鋁相比較時,他們有較高的抗電遷移性(resistance against electromigration)和相當低的電阻率(electrical resistivity)之優越特性。關於在半導體工廠中之處理和操作,銅雖然有這些優點,但是其亦呈現了許多的缺點。例如,由於銅的形成非揮發性反應產品之特性,銅不能用廣為接受的沉積方法(譬如化學氣相沉積法(CVD)和物理氣相沉積法(PVD))來有效地大量應用到基板上,並亦不能用常用之非等向性蝕刻(anisotropic etch)過程來有效地圖案化。於製造包含銅之金屬化層時,因此最好是使用所謂的金屬鑲嵌(damascene inlaid)技術,其中首先應用電介質層,然後圖案化以定義在其中之溝槽和通孔(via),接著將該等溝槽和通孔用譬如銅之金屬將其填滿。
銅的進一步主要缺點是其易擴散於二氧化矽和其他電介質材料中之傾向。因此通常需要使用所謂之障壁材料(barrier material)結合銅基金屬化(copper-based metallization)以實質避免銅任何的向外擴散(out-diffusion)進入周圍的電介質材料,如此則銅可容易遷移至敏感的半導體區域,因而明顯地改變其特性。再者,由於銅之完整性(integrity),可選擇障壁材料以抑制不需要之材料譬如氧、氟等之向銅擴散,因而減少腐蝕和氧化作用之風險。因為溝槽和通孔之尺寸現已達到約0.1 μ m和甚至更短之寬度或直徑,具有大約5或更大之通孔縱橫比,於通孔和溝槽之所有表面上之障壁層的可靠沉積,及後續的用銅填滿其通孔而大致沒有空隙(void)是現代積體電路製造中最大挑戰之問題。
現今,藉由圖案化適當的電介質層和藉由譬如濺鍍沉積(sputter deposition)之先進物理氣相沉積(PVD)技術沉積障壁層(例如,包含鉭(Ta)和/或氮化鉭(TaN)),而完成銅基金屬化層之形成。對於沉積大約10至50 nm之障壁層於具有5或更大縱橫比之通孔中,通常使用增強之濺鍍工具。此等工具在將靶材(target)原子濺鍍離開靶材後,提供離子化希望比值的靶材原子的可能性,因而使得能夠控制於通孔中底部覆蓋範圍和側壁覆蓋範圍至某一程度。其後,銅被填滿於通孔和溝槽中,其中已證明電鍍是可用的製程技術,因為電鍍相較於CVD和PVD之速率,能夠以一種所謂之自底向上方式(bottom-up regime)以高的沉積速率填滿通孔和溝渠,其中開口以實質上無空隙方式於底部開始充填。一般而言,於電鍍金屬時,外部電場施加於將被電鍍之表面和電鍍溶液之間。因為用於半導體生產之基板能接觸於受限制之區域(通常在基板之周邊),因此必須提供涵蓋基板和接收金屬之表面之導電層。雖然先前沉積在圖案化電介質之上之障壁層可作用為電流分佈層,然而,結果是,鑑於結晶度(crystallinity)、一致性和黏著特性,所謂的晶種層(seed layer)通常要求於後續的電鍍製程中獲得具有所需電和機械特性之銅溝槽和通孔。通常包括銅之晶種層一般係藉由濺鍍沉積而實施,該濺鍍沉積使用與用於障壁層之沉積實質相同的製程工具。
於未來世代裝置之0.1μm和更小尺寸之通孔中,具有高度符合障壁層和晶種層需求之極薄金屬層之濺鍍沉積可變成限制因素,因為若沒有明顯修正這些工具則也許不會進一步增強上述先進濺鍍工具之階梯覆蓋特性(step coverage characteristic),此情況似乎並非簡單的發展。尤其是,晶種層的沉積可不由PVD以簡單的方式實施,如此處晶種層之一致性決定後續之電鍍製程之一致性至某一程度,相反於障壁層“僅”要求開口之內表面之充分和完全之覆蓋。而且,產生適用於障壁層之極薄層之PVD技術當應用於形成晶種層時可造成增加之電阻,因而減少後續電鍍製程之初始沉積率。
結果,已提出用於高度複雜應用之替代沉積技術用於銅基線之障壁沉積和晶種沉積。例如,已發展出CVD技術用來形成高度共形(conformal)障壁和晶種層,因而利用有關相較於濺鍍沉積之階梯覆蓋CVD固有優越性能之優點。同樣情況,已發展已知為原子層沉積(atomic layer deposition;ALD)之自我限制基於CVD沉積(self-limiting CVD-based deposition)技術用於數種材料以便在高縱橫比開口內提供極薄但可靠的障壁或晶種層。然而,雖然本身提供了關於層黏稠和覆蓋(layer consistency and coverage)之優點,於後續的電鍍製程
後,似乎這些技術造成較不希望之銅金屬性能。尤其是,由於引入了相當的污染,晶種層也許較差於廣泛使用的PVD晶種層,因而造成較高的電阻和較弱之材質(texture)從而導致近似隨機圖案化之金屬膜。
有鑑於上述之情況,因此需要一種增強之技術使能在高縱橫比開口內藉由濕式化學沉積製程有效地沉積金屬,因而避免或至少減少上述之一個或多個問題。
以下提出本發明之簡化概要以提供本發明之一些態樣的基礎瞭解。此概要不是本發明徹底的概觀。該概要並非要識別本發明之關鍵或緊要元件或描述本發明之範圍。其唯一目的係以簡化的方式提出一些概念作為前言,而更詳細的說明會稍後討論。
一般而言,本發明係針對一種能夠形成填滿金屬之開口之技術,該等開口形成於圖案化電介質層中,其中使用濕式化學沉積製程至少用於填滿於基體金屬(bulk metal),其中,於一些例示實施例中,於一些應用中也許需要之障壁層亦可藉由濕式化學沉積製程來形成。如此一來,可克服用來形成障壁和/或晶種層之譬如濺鍍沉積之物理氣相沉積技術之限制,因而提供進一步裝置縮放尺寸而實質上不會過度減損效能之可能。於本發明之一些實施例中,藉由形成適度薄之共形層(其可作用為晶種層),可沉積譬如銅、銀等之適當金屬於個別開口中,然後可於原位改變各自的沉積參數以達成其餘沉積製程所希望之自底至頂充填行為(bottom-to-up fill behavior)。結果,以此種方式,因為可獲得最終沉積金屬所希望之結晶度(crystallinity),因此可達成增強之效能,而另一方面,對於在習知技術中於形成晶種層後可能遭遇到之金屬腐蝕或氧化作用之任何不良的影響,可實質避免掉或至少顯著地減少。
依照本發明的一個例示實施例,一種方法包括:藉由施加電解液和施行無電濕式化學沉積製程而在半導體裝置之圖案化層之上沉積金屬。再者,該方法包括於電解液中建立外部產生電場,同時施加電解液以便進一步沉積金屬。
依照本發明的另一個例示實施例,一種方法包括:藉由濕式化學沉積製程在半導體裝置之電介質層中所形成之開口之表面部分之上形成障壁層。而且,藉由濕式化學沉積製程在障壁層之上形成晶種層,並最後藉由使用該晶種層之電鍍製程用金屬填滿該開口。
以下說明本發明之例示實施例。為求清楚,本說明書並未說明實際實作之所有特徵。當然,我們當瞭解,在開發任何此種實際的實施例時,必須作出許多與實施例相關之決定,以便達到開發者的特定目標,譬如符合隨著實施例的不同而有所變化的與系統相關及與商業相關之限制條件。此外,我們應當瞭解,此種開發工作可能是複雜且耗時的,然而,對已從本發明的揭示事項獲益的該技術領域中具有通常知識者而言,仍將是一種例行工作。
現將參考附圖來說明本發明。各種結構、系統和裝置係示意地繪示於圖式中僅為了說明之目的,以便不會由熟悉此項技術者已熟知之細部而模糊了本發明。不過,仍包括附圖來說明與解釋本發明之實例。應以熟悉該項技藝者所認定之意義來瞭解與解釋本文中的字彙與詞。本文前後一致使用的術語以及詞彙並無暗示特別的定義,特別定義係指與熟悉該項技藝者認知之普通慣用的定義所不同之定義。如果一個術語或詞彙具有特別定義,亦即非為熟悉該項技藝者所瞭解之意義時,本說明書將會以定義的方式直接且明確地提供其特殊定義。
本發明提供一種根據鑲嵌或金屬鑲嵌技術形成金屬填滿開口之改進技術,其中首先圖案化層以收容任何開口,譬如溝槽、通孔、閘極開口等,該等開口將後續用譬如銅、銀、他們的合金等之高導電金屬填滿。如前面的說明,雖然具有關於材料污染及成本效益的優點,習知技術事實上存在著明顯的缺點,如物理氣相沉積技術對於包含明顯小於0.1μm特徵尺寸之裝置世代會遭到嚴重的困難。結果,譬如銅晶種層(其為有效填入(fill-in)製程之基礎)之晶種層之可靠和高均勻沉積也許不易藉由現今的濺鍍沉積技術而予完成。同樣狀況,譬如CVD、ALD等之高度先進的沉積技術也許造成減少之結晶度和增加污染程度,由此增加所得金屬區之全部電阻值,此情況直接轉化成減少整個半導體裝置之效能。
本發明藉由提供可由濕式化學沉積製程形成晶種層之技術而防止或至少減少上述討論之一些問題。其中,於一些例示實施例中,額外地,適當的障壁層亦可根據濕式化學沉積製程而形成。如此一來,可完成形成障壁層和晶種層之高度一致性和可靠性,即使對於高度縮放尺寸之半導體裝置亦然,同時於另一方面,可根據濕式化學沉積製程而獲得晶種層之所希望之表面材質,因而提供了用於後續充填於基體金屬之有效的基底層(base layer)。於本發明之其他實施例中,充填的金屬譬如銅、銀等,可於濕式化學沉積製程中完成,其中可由催化劑反應(catalytic reaction)初始或至少明顯地促進金屬沉積,然後催化劑反應於沉積製程之稍後階段由電鍍沉積方式(electroplating deposition regime)所“超控(overrule)”,其中適當地選擇製程參數以獲得所希望之自底至頂充填行為,以便提供實質的無空隙高度導電金屬區,於此區中可明顯地減少譬如氧化作用、腐蝕等之任何的不良效果,這是因為金屬之初始沉積材料層可作用為晶種層用於沉積製程之電鍍主導階段(electroplating-dominated phase)。於一些例示實施例中,充填之金屬可以於原位製程(in situ process)完成,其中第一階段為無電沉積製程,其中金屬沉積由將被充填之開口之暴露表面部分上所提供之催化劑材料所驅動。其後,可在濕式化學沉積環境內建立外部產生之電場,以根據電場(亦即,根據被驅動流經沉積環境之電流)和根據包含於該濕式化學沉積環境中任何適當選擇之附加條件來實質控制沉積動能。
應了解到本發明高度有利於結合具有0.1 μ m和明顯更小之關鍵尺寸(critical dimension)之高度縮放尺寸之半導體裝置或任何其他的微結構,例如可於具有50nm和甚至更短之閘極長度之場效電晶體之複雜積體電路中之情況時。然而,本發明亦可應用於較不緊要之設備,其中任何金屬化層之優異品質可明顯地貢獻這些較不緊要半導體裝置增進之可靠性和效能。結果,除非在其他方面特定於進一步實施方式中和於所附申請專利範圍中,否則本發明不應被推斷為受限於特定的裝置尺寸。
於第1a圖中顯示半導體裝置100並表示收容具有典型用於微結構之尺寸之填滿金屬之特徵之任何的適當裝置。於本實施例中,半導體裝置100可表示含有複數個電路元件(譬如電晶體、電容器、電阻器等)之積體電路,其中至少一些該等電路元件具有大約50nm或甚至更小之關鍵尺寸。為了方便,任何之此等電路元件都未顯示於第1a圖中。再者,半導體裝置100包括基板101,該基板101上形成有譬如指示為102之電介質層之第一層,該第一層可包含導電線或含有金屬區103之區104。例如,於複雜之應用設備中,金屬區103可包括銅、銅合金、銀、鎢、或一般用於半導體裝置之任何其他適當的導電金屬。於一個例示實施例中,金屬區103可包括銅、銀等,其中該金屬區103可藉由障壁層105而與層102之周圍之電介質材料分隔。障壁層105可包括任何適當的材料,譬如鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢,或任何其他具有關於幫助金屬區103擁有所需機械和化學完整性所希望特性之適當的化合物。於一些例示實施例中,障壁層105可由一種或多種下列化合物組成:鈷、鎢、磷(CoWP);和/或鈷、鎢、硼(CoWB)和/或鈷、硼(CoB)和/或鉬、鎳、硼(MoNiB),等等。應了解到,導電線104僅例示性質,其可表示一種依照金屬鑲嵌技術,用於形成先進的半導體裝置之金屬化層所形成之典型的結構。於其他的實施例中,導電線104可表示任何需要形成通孔或連接至該通孔之溝槽之電路元件。例如,導電線104可表示直接連接到電路元件之接觸區之接觸插塞(contact plug),或導電線可表示譬如汲極或源極區、閘極電極等之電路元件之接觸區。
第二電介質層107,其可包括任何適當的材料(譬如二氧化矽、氮化矽),或任何低k材料(譬如SiCOH),或任何其他的材料(譬如適當的聚合物),而可形成在第一電介質層102之上,其中連接至金屬區103之譬如溝槽或通孔之開口108係形成於第二電介質層107中。如前面之說明,於一些例示實施例中,開口108可以表示高縱橫比開口,該開口於至少一個橫向尺寸(譬如寬或直徑)明顯地小於開口108之深度。如此一來,橫向尺寸(亦即,於第1a圖中開口108之水平延伸區)可以約100nm和明顯更小,而開口108之深度可為幾百nm。然而,應了解到,於其他例示實施例中,開口108可以有其他的尺寸,而對應的縱橫比也許少於大約5。
再者,於電介質層107之暴露表面部分107A和開口108內,提供有催化活化材料之區域112。於一個實施例中,可表示暴露表面部分107A之區域之區域112可已包含任何催化劑材料於其中,該任何催化劑材料係適用於初始障壁材料之後續濕化學沉積。於另外其他的實施例中,區域112可表示實質連續的材料層,其可包括具有適用於作用為用於將充填於開口108中之金屬(譬如銅、銀等)之障壁材料之特性之適當的導電材料。以此方式,層112亦可包含某一數量之催化劑材料,譬如鈷、銀、鈀、鉑、銅等等,該材料可用於後續之銅、銀等濕式化學沉積。應了解到,於此情況,催化劑材料可不以大致連續之方式覆蓋所有的暴露表面部分107A,但是可以併入足夠的密度用於初始後續之濕式化學沉積。於另外其他的例示實施例中,區域112可表示具有一層催化劑材料形成於其上之障壁層,該催化劑材料包括上述特定種類之至少其中一種作用為用於後續沉積銅、銀等充填該開口108。
於另外其他的例示實施例中,催化活化區域112可表示連續的層,或具有鈀併入於其中之至少表面部分,於一個實施例中,或可作用為用於障壁材料之後續濕式化學沉積之催化劑材料之其他適當的催化劑。
用來形成顯示於第1a圖中半導體裝置100之典型製程流程可包括下列製程。於基板101中或上製造任何電路元件或其他微結構特徵之後,導電線104可形成於第一電介質層102,其中,於一些例示實施例中,導電線104可依照亦將稍後說明於當參照充填該開口108之沉積製程之相同的製程技術而形成。因此,關於形成障壁層105和金屬區103,可應用如稍後討論之相同的標準。然而,應了解到,於其他的例示實施例中,導電線104可依照廣為接受用以形成電路元件、接觸區等之習知的製程技術形成。其後,依於用於層107之材料或各材料之類型,可藉由例如CVD、旋塗(spin-on)技術等而沉積第二電介質層107。應了解到電介質層107可依照裝置需求而包括二種或多種不同之材料,其中可在形成電介質層107之前沉積額外的蝕刻終止層(未顯示)。隨後,可根據廣為接受的製程方法之適當光微影術(photolithography)和非等向性蝕刻(anisotropic)技術而形成開口108。其後,於一個例示實施例中,半導體裝置100可經受催化活化製程116以便形成區域112。為此目的,活化製程116可包括浸沒(immersion)或噴灑(spray)製程,根據接受之技術應用適當的催化劑材料於暴露之表面部分107A。於一個例示實施例中,含鈀溶液可用來形成催化活化區域112。於其他例示實施例中,活化製程116可施行為沉積製程,例如根據CVD、ALD、PVD,以便形成包括譬如鈀之適當催化劑材料之薄材料層,其中只要足夠量之催化劑材料提供於暴露表面部分107A,則製程之階梯覆蓋較不緊要。例如,可根據CVD技術形成高度均勻且薄的層,其中,於一些實施例中,在製程116之前,可施行對應的清洗製程(例如從金屬區103之暴露表面去除任何的污染和氧化部分),因而減少於後續的製程期間併入污染物之風險。於另外其他的例示實施例中,區域112可形成為障壁層,例如根據鉭、氮化鉭、鈦、氮化鈦、鎢,並可由廣為接受之濺鍍沉積技術形成,其中適當的催化劑材料可併入層112中,使能施行後續用於高導電金屬(譬如銅、銀等)之濕式化學沉積製程,然後其可以單一充填製程沉積,如將於稍後說明者。
第1b圖示意地顯示於進一步先進製造階段之半導體裝置100。於此例示實施例中,障壁層110形成於電介質層107之暴露表面部分107A上和開口108內。於一個例示實施例中,障壁層110可包括可根據濕式化學沉積製程117沉積之材料。於一個例示實施例中,障壁層110可由包括鈷鎢磷(CoWP)和/或鈷鎢硼(CoWB);鈷硼(CoB),鉬鎳硼(MoNiB)之一個或多個化合物組成。依照製程和裝置需求,障壁層110能設以適當的厚度。例如,於複雜之應用中,厚度於約5至50 nm之範圍也許適當。
如參照區域112之前面的討論,在與濕式化學沉積環境117接觸後,其中催化活化表面部分初始減少包含於該環境117中之對應金屬離子,該環境117可以適當電解液之形式提供,因而形成障壁層110。可基於譬如電鍍反應器、噴灑工具等之可取得的製程工具,而由浸沒或噴灑製程之方式提供電解液117。層110之材料之沉積例如可以基於沉積速率而控制,該沉積速率可根據進行的測試而事先建立。再者,於其他的例示實施例中,可根據環境117和/或基板101之溫度而控制製程,其中可有效地控制正與區域112接觸之電解液之溫度。為達此目的,當以電解池(electrolyte bath)形式建立環境117時,池溫度可保持於稍微低於自行催化反應之臨界溫度之特定溫度,因而避免了於對應之反應室中金屬之任何過度的自發創生(spontaneous creation)。為了初始反應,可加熱基板101以便提供所希望之表面溫度,因而亦升高正與區域112接觸之電解液之溫度至所需之活化溫度以初始電化學沉積。
當沉積層110至所希望之厚度後,基板101溫度可降低,因而明顯放慢或甚至完全停止任何進一步之沉積。因為可在適度短的時間間隔內建立基板101之溫度改變,因此可有效地控制基於基板溫度之沉積製程117。而且,當以電解池之形式提供沉積環境117時,可持續地保持池溫度低於臨界溫度,同時仍然允許高度有效之材料沉積,只要基板溫度維持於所希望之製程溫度即可。例如,於電化學沉積層110可使用典型約50至90℃之製程溫度,其中池溫度可維持於大約40至50℃,同時基板101溫度增加至例如50至90℃。當根據噴灑製程工具建立沉積環境117時,可以特定的製程溫度或高於特定的製程溫度之溫度施加對應之電解液,以便一旦接觸催化活化區域112便初始材料沉積。於其他的實施例中,可用噴灑製程工具以低於臨界溫度之溫度來供應電解液,而可控制基板101溫度以便“接通(switch on)或關斷(switch off)”沉積製程。例如,可以大致“立即地”冷卻和加熱電解液容積之方式而適當地選擇電解液容積。例如,對每個基板可使用大約達200ml之電解液容積。
於一些例示實施例中,可配置濕式化學沉積製程117而使得所希望之催化劑材料併入層110中(至少於其表面部分),以便製備障壁層110,用於後續之濕式化學沉積製程,以高導電金屬填滿開口108。例如,環境117之電解液可包括鈷、銀、鈀、鉑、銅其中之一種或多種,該等金屬可作用為後續金屬沉積之催化材料。又於其他的實施例中,於沉積層110後,和於任何清洗和乾燥製程後,可對障壁層110施行進一步之催化活化製程以提供適度之活化表面部分用於後續的導電金屬的充填。如前面參照第1a圖之解釋,當區域112已說明也作用為障壁層時,亦可施行對應之製程以提供具有所希望之催化劑特性之障壁層110。例如,於一個例示實施例中,可藉由CVD、ALD或PVD而沉積額外的層,其中,如前面之討論,因為對應形成之催化劑材料可不需繼續覆蓋障壁層110,故階梯覆蓋較不緊要。於其他例示實施例中,障壁層110可暴露於包含至少一種催化劑種類之電漿環境中,該催化劑可併入該障壁層110之表面部分中。
第1c圖示意地顯示於進一步先進製造階段之半導體裝置100。於一個例示實施例中,半導體裝置100經受濕式化學沉積環境118,該環境配置以使能夠沉積譬如銅之高導電金屬,而又於其他的實施例中,譬如銀等之其他金屬可包含於環境118中。可以電解液之形式提供濕式化學沉積環境118,該電解液藉由譬如電解池反應器(bath reactor)、噴灑工具等任何適當的製程工具而施加至裝置100之暴露表面。因此,環境118之電解液可包括將被沉積之金屬鹽和適當減少之媒介。例如,當將要沉積銅時,可使用銅、EDTA、NaOH和HCHO;銅、KNa酒石酸(tartrate)、NaOH、HCHO、等等形式之適當的電解液組合物。再者,環境118之電解液可包括適當的添加劑,該添加劑能明顯改變沉積動能,表現於外部產生之電場,稍後將作更詳細之說明。
如所熟知的,對於可靠的充填於電介質材料中之高縱橫比開口,例如用銅或銅合金,一般需要所謂之自底至頂充填行為,其可根據適當的脈衝電流方式和個別的添加劑而達成。已了解到所需之填入行為可藉由引入添加劑於電解液中來控制在通孔(譬如開口108)內之沉積動能以影響銅離子沉積在個別位置之速率而獲得。例如,包括相對大、擴散慢之分子(譬如聚乙二醇)之有機媒介可加至電解液中,而使得對應之分子能優先地於平坦表面和角落部分吸收,因而減少銅離子於這些區域之接觸,而因此亦減少沉積速率。對應作用媒介時常稱之為“抑制劑(suppressor)”。另一方面,可使用包括較小和較快速擴散分子之另外的添加劑,該添加劑優先地在高縱橫比開口(譬如開口108)內吸收,而藉由補償抑制劑添加劑之效果而增強沉積率。對應之添加劑經常稱之為“加速劑(accelerator)”。而且,依照製程和裝置需要,可併入其他的添加劑至環境118之電解液中。選用以上述方式能明顯改變沉積動能之添加劑,而使得於典型的苛性環境(caustic environment)亦獲得所希望之加速和抑制特性,如於環境118中之初始沉積階段所需者。
如前面之說明,當暴露於濕式化學環境118時,障壁層110可包含(至少於其表面部分)作用為用於金屬沉積之催化劑之材料。如此一來,根據環境118之電解液與催化活化障壁層110之接觸,可形成層113,其中,由於沉積行為,層113可以高度共形方式形成,因為於此階段之沉積製程,環境118可視為用於無電沉積製程之濕式化學沉積環境。於是,於此初始沉積階段期間形成金屬化層113可視為用於後續沉積階段之晶種層,在適當的外部產生之電場中可施行該金屬化層113以依照所需電鍍方式建立電流流動。於一個例示實施例中,可維持濕式化學沉積製程118之無電階段以形成具有厚度約1至50 nm之層113。根據製程時間控制可完成對應之厚度控制,可藉由產生特定的電流流動,於環境118中沒有外部產生電場而經過特定沉積時間後,而達成此製程時間控制。於用來形成晶種層113之金屬沉積之初始階段,可控制環境118之製程溫度以使能夠有效的材料沉積。關於溫度控制,應用如前面參照沉積環境117說明之相同的準則。也就是說,於一些例示實施例中,可控制環境118之電解液之溫度和/或基板101溫度以達成特定的製程溫度,例如,其可以是在約60至100℃之範圍。於一個例示實施例中,電解液之溫度(其可以電解池等之形式提供)可以維持低於特定之臨界製程溫度,譬如約60℃,同時基板101溫度可以維持在或高於特定之製程溫度。如此一來,只要裝置100之暴露表面部分之緊鄰附近的電解液之溫度是在或高於特定的製程溫度時,即獲得有效之金屬沉積,其中可根據製程溫度而有效地控制此階段期間實質之共形沉積,使得於形成晶種層113之所希望的共形沉積階段後,製程溫度可顯著地降低,以便有效地減少或避免進一步之共形沉積。應了解到,包含於環境118之電解液中之添加劑可大致表示雙極(dipole)分子,對外部產生之電場反應,同時實質上不影響於初始沉積階段用來形成晶種層113之沉積行為,除了與其他組成部分和暴露表面部分(亦即,暴露於環境118之層110)建立吸收/脫附(desorption)平衡之外。
其後,可建立適當的電流流動以繼續進一步之金屬沉積,與具有自底至頂充填行為之廣為接受的電鍍製程中已知者相似。於一些例示實施例中,可根據外部產生電場建立濕式化學沉積製程118,其中可適當地控制可經由導電障壁層110獲得的對應電流流動,以藉由調整無電沉積方式和電鍍沉積方式之影響比例而稍微修改於形成晶種層113期間之沉積行為。也就是說,藉由對應地調整製程溫度和建立適當的電流流動(其可被選擇以便仍保持由無電方式所主導之沉積行為),可完成更非等向性的沉積行為。例如,由於外部產生之電場,添加劑之性質可被“活化”至某程度,因而,例如,提高增加之沉積於開口108之底部111,同時仍提供適當的共形沉積於裝置100之其他表面部分。當經考慮認為適當時,可於沉積製程之任何時間點建立對應共存之無電和電鍍方式。例如,可如上之討論建立高度共形初始沉積階段,而其後可建立某一轉移階段,以便藉由增強於開口108之底部111之沉積率而進一步增加晶種層113之厚度,同時仍放鬆對於後續自底至頂充填製程之抑制。最後,當獲得所希望之晶種層113之厚度時,製程控制可被“切換”至純電鍍方式。
第1d圖示意地顯示半導體裝置100,其中濕式化學沉積環境118是處在電鍍方式。於是,外部產生之電場119建立於環境118中,因而引發電流120流經環境118之電解液。此外,根據電鍍方式,形成金屬層114以實質上完全填滿開口108,其中過多的材料亦可沉積於裝置100之水平表面部分。於第1d圖中所示電鍍方式期間,可根據任何適當的策略(譬如電位-靜態/動態(potentio-static/dynamic)或電流-靜態/動態(galvano-static/dynamic)沉積技術),而建立電場119和因此引發之電流120。於對應之電流脈衝方式期間,包含於沉積環境118中之添加劑現在提供所需的自底至頂充填行為,如由習知和廣為接受之電鍍製程所已知者。於一個例示實施例中,當從無電控制方式轉移至第1d圖之電鍍方式時,降低了環境118之電解液之溫度和基板101溫度,因而有效地減少或消除任何之共形沉積行為,使得沉積動能實質由電鍍方式所控制。例如,電解液和基板101之溫度可降低至約40℃或更低,以實質終止無電沉積製程。
結果,可根據具有所希望之表面材質之晶種層113而形成金屬層114,其中,如經常於先進CVD或ALD技術中所遭遇的,由於形成晶種層113和最終金屬層114之製程的原位的性質,而可明顯地減少晶種層之污染。
於另外其他的實施例中,可基於障壁層110而於分離沉積製程中形成晶種層113,該晶種層113亦可基於濕式化學沉積製程而形成,例如,當晶種層113可由相較於金屬層114之不同的材料組成時。於此種製程策略中,由於障壁層110與晶種層113之電化學沉積而可獲得明顯的優點,因而提供了進一步之裝置縮小的可能性,同時關於形成金屬層114仍達成高度的製程彈性,因為此處可於高度共形且可靠的晶種層113上施行分離的沉積製程。
於另外其他的例示實施例中,根據如上述參照第1c和1d圖之濕式化學沉積製程118,晶種層113和金屬層114之沉積亦可用於結合根據其他沉積技術(譬如CVD、ALD或PVD)所形成之障壁層,如前面參照第1a圖之說明當有關催化活化區域112作為障壁層時。如上之討論,於此等情況中,障壁層112然後可包括個別的催化劑材料,或對應之催化劑材料可形成於層112上。
因此,本發明提供了一種根據嵌入技術用來形成高導電金屬區之加強技術,其中根據濕式化學沉積製程而形成晶種層,於一個例示實施例中,該濕式化學沉積製程結合後續的電鍍製程,並同時連續地暴露該裝置於適當設計的電解液中。於此情況,提供原位製程(in situ process),其中於電鍍方式期間適當選擇之添加劑提供所希望之自底至頂充填行為,同時此等添加劑於形成晶種層期間係實質
上“不作用(inactive)”。而且,可根據濕式化學沉積製程而形成障壁層,然後該障壁層可作用為晶種層或催化層,用於初始欲充填入甚至更小尺寸的半導體裝置之個別開口之高導電金屬之濕式化學沉積。如此一來,當使用廣為接受之整合概念時,本發明能夠形成用於45nm技術模式以及甚至更窄之互連結構的金屬化,而實質上不會減損裝置效能。再者,本發明可使用結合複數種金屬,譬如銅、銀等。
以上揭示之特定實施例僅為例示性之說明,然對於熟悉此項技術者於了解本說明書之內容後可很顯然地了解本發明可用不同但等效之方式作修改或實作。舉例來說,前述之處理步驟可以不同之順序來執行。再者,除了後述之申請專利範圍所描述者外,其於此顯示之詳細構造或設計並非要用來限制本發明。因此很明顯的,以上所揭露之特定實施例可在不違背本發明之精神及範疇下進行修飾與改變,而所有之此等改變皆考慮在本發明之精神與範圍內。由是,本發明之權利保護範圍,應如後述之申請專利範圍。
100...半導體裝置、裝置
101...基板
102...第一電介質層、層
103...導電線(金屬區)
104...區(導電線)
105...障壁層
107...第二電介質層、層、介電層
107A...暴露表面部分
108...開口
110...障壁層、層
111...底部
112...催化活化區域(層)、區域、障壁層
113...金屬化層(晶種層)、層
114...金屬層
116...活化製程、催化活化製程、製程
117...濕式化學沉積製程(濕式化學沉積環境)(電解液)、環境、沉積環境
118...濕式化學沉積環境、環境
119...外部產生電場、電場
120...電流
藉由參照上述之說明配合所附之圖式可以了解本發明,於各圖式中相同的元件符號表示相同的元件,且其中:第1a至1d圖示意地顯示依照本發明之例示實施例在填滿形成在圖案化電介質層中之開口之各種製造階段期間半導體裝置之剖面圖。
雖然本發明容許作各種之修飾和替代形式,但在此係由圖式中之例子顯示及詳細說明本發明之特定實施例。然而,應暸解到此處特定實施例之圖式及詳細說明並不意欲用來限制本發明為所揭示之特定形式,反之,本發明將涵蓋所有落於如所附申請專利範圍內所界定之本發明之精神和範圍內之修飾、等效和替代內容。
100...半導體裝置、裝置
101...基板
102...第一電介質層、層
103...導電線(金屬區)
104...區(導電線)
105...障壁層
107...第二電介質層、層、介電層
108...開口
110...障壁層、層
111...底部
113...金屬化層(晶種層)、層
114...金屬層
118...濕式化學沉積環境、環境
119...外部產生電場、電場
120...電流
Claims (24)
- 一種製造積體電路之方法,包括下列步驟:藉由施加電解液和施行無電濕式化學沉積製程而在半導體裝置之圖案化層之上沉積金屬的第一部分;於該電解液中建立外部產生電場,同時施加該電解液以便藉由電鍍沉積製程進一步沉積該金屬的第二部分;於沉積該金屬之前,在圖案化電介質材料上形成障壁層,該圖案化電介質材料和該障壁層形成該圖案化層;以及於施行該無電濕式化學沉積製程之前,先對該圖案化層之暴露表面區域施行催化活化製程。
- 如申請專利範圍第1項之方法,其中,施行該催化活化製程包括將鉑、鈀、銀、銅和鈷之至少其中一種併入於至少一些之該暴露表面區域中。
- 如申請專利範圍第1項之方法,其中,當形成該障壁層時,將鉑、鈀、銀、銅和鈷之該至少其中一種併入於該障壁層中。
- 如申請專利範圍第1項之方法,其中,於形成該障壁層後,將鉑、鈀、銀、銅和鈷之該至少其中一種併入於該障壁層中。
- 如申請專利範圍第1項之方法,復包括於沉積該金屬之前,在該障壁層之上形成催化層。
- 如申請專利範圍第5項之方法,其中該催化層藉由化學 氣相沉積、物理氣相沉積和原子層沉積之至少其中一種所形成。
- 如申請專利範圍第1項之方法,其中該障壁層藉由無電沉積製程所形成。
- 如申請專利範圍第7項之方法,復包括於形成該障壁層之前,對該圖案化電介質材料之暴露表面區域施行初始催化活化製程。
- 如申請專利範圍第8項之方法,其中,施行該初始催化活化製程包括將催化劑材料併入於該暴露表面部分以用來初始該障壁層之材料之沉積。
- 如申請專利範圍第1項之方法,其中該障壁層包括至少一種下列之化合物:含有鈷、鎢、磷之化合物;含有鈷、鎢、硼之化合物;含有鈷、硼之化合物;和含有鉬、鎳、硼之化合物。
- 如申請專利範圍第1項之方法,其中於建立該電場用於進一步沉積該金屬之前,於該無電濕化學沉積製程期間沉積該金屬大約1至10nm之厚度範圍。
- 如申請專利範圍第1項之方法,其中該電解液包括一種或多種添加劑用於控制在根據該電場之進一步沉積期間的沉積行為,其中,該添加劑係抑制劑或加速劑。
- 如申請專利範圍第1項之方法,復包括當根據該電場進一步沉積該金屬時,降低該電解液之溫度低於該無電沉積製程之特定製程溫度。
- 如申請專利範圍第13項之方法,其中該溫度降低至約 40℃或更低。
- 如申請專利範圍第13項之方法,其中於建立該外部產生電場之前降低該溫度。
- 如申請專利範圍第1項之方法,其中該金屬包括銅和銀之至少其中一種。
- 如申請專利範圍第1項之方法,,復包括下列步驟:藉由濕式化學沉積製程形成該障壁層,以在該半導體裝置之該電介質層中所形成之開口形成襯裡(line);藉由濕式化學沉積製程在該障壁層之上形成晶種層;以及藉由使用該晶種層之電鍍製程用金屬填滿該開口。
- 如申請專利範圍第17項之方法,復包括於用於形成該晶種層之該濕式化學沉積製程期間對該障壁層施行催化活化製程以用於初始金屬沉積。
- 如申請專利範圍第18項之方法,其中,形成該晶種層和填滿該開口被施行為原位製程。
- 如申請專利範圍第19項之方法,其中,於填滿該開口期間降低用來形成該晶種層和用來填滿該開口之電解液之製程溫度。
- 如申請專利範圍第18項之方法,其中,當形成該障壁層時,將鉑、鈀、銀、銅和鈷之該至少其中一種併入於該障壁層中。
- 如申請專利範圍第18項之方法,其中,於形成該障壁層後,將鉑、鈀、銀、銅和鈷之該至少其中一種併入於 該障壁層中。
- 如申請專利範圍第19項之方法,其中,於形成該晶種層期間至少暫時地建立外部產生電場。
- 如申請專利範圍第17項之方法,其中該障壁層包括至少一種下列之化合物:含有鈷、鎢、磷之化合物;含有鈷、鎢、硼之化合物;含有鈷、硼之化合物;和含有鉬、鎳、硼之化合物。
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US11/536,041 US7517782B2 (en) | 2005-12-30 | 2006-09-28 | Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase |
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DE102007004884A1 (de) * | 2007-01-31 | 2008-08-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht |
US20080261392A1 (en) * | 2007-04-23 | 2008-10-23 | John Trezza | Conductive via formation |
JP4647020B2 (ja) | 2009-07-30 | 2011-03-09 | キヤノン株式会社 | 窒化物半導体の微細構造の製造方法 |
DE102010003556B4 (de) * | 2010-03-31 | 2012-06-21 | Globalfoundries Dresden Module One Llc & Co. Kg | Verfahren zur Herstellung von Kontaktelementen eines Halbleiterbauelements durch stromloses Plattieren und Entfernung von überschüssigem Material mit geringeren Scherkräften |
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CN103094193B (zh) * | 2011-11-02 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | 一种铜互连结构的制造方法 |
JP6270681B2 (ja) * | 2014-09-29 | 2018-01-31 | 学校法人 関西大学 | 配線構造体の製造方法、銅置換めっき液および配線構造体 |
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US9837312B1 (en) * | 2016-07-22 | 2017-12-05 | Lam Research Corporation | Atomic layer etching for enhanced bottom-up feature fill |
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US20070166982A1 (en) | 2007-07-19 |
GB2446750B (en) | 2010-11-17 |
TW200732509A (en) | 2007-09-01 |
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