JP5404685B2 - 不揮発性半導体記憶装置 - Google Patents

不揮発性半導体記憶装置 Download PDF

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Publication number
JP5404685B2
JP5404685B2 JP2011084762A JP2011084762A JP5404685B2 JP 5404685 B2 JP5404685 B2 JP 5404685B2 JP 2011084762 A JP2011084762 A JP 2011084762A JP 2011084762 A JP2011084762 A JP 2011084762A JP 5404685 B2 JP5404685 B2 JP 5404685B2
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Japan
Prior art keywords
voltage
read operation
read
memory cell
value
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JP2011084762A
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English (en)
Japanese (ja)
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JP2012221522A (ja
JP2012221522A5 (enExample
Inventor
泰洋 椎野
栄悦 高橋
広貴 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2011084762A priority Critical patent/JP5404685B2/ja
Priority to US13/246,004 priority patent/US8385126B2/en
Publication of JP2012221522A publication Critical patent/JP2012221522A/ja
Priority to US13/749,029 priority patent/US8649221B2/en
Publication of JP2012221522A5 publication Critical patent/JP2012221522A5/ja
Priority to US14/088,744 priority patent/US9025387B2/en
Application granted granted Critical
Publication of JP5404685B2 publication Critical patent/JP5404685B2/ja
Priority to US14/677,111 priority patent/US9472295B2/en
Priority to US15/263,518 priority patent/US9691489B2/en
Priority to US15/598,554 priority patent/US9947415B2/en
Priority to US15/915,129 priority patent/US10186321B2/en
Priority to US16/209,520 priority patent/US10490286B2/en
Priority to US16/597,242 priority patent/US10818362B2/en
Priority to US17/026,904 priority patent/US11004520B2/en
Priority to US17/219,003 priority patent/US11621041B2/en
Priority to US18/173,211 priority patent/US11817155B2/en
Priority to US18/467,793 priority patent/US12068040B2/en
Priority to US18/752,870 priority patent/US12322454B2/en
Priority to US19/196,186 priority patent/US20250273276A1/en
Active legal-status Critical Current
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
JP2011084762A 2011-04-06 2011-04-06 不揮発性半導体記憶装置 Active JP5404685B2 (ja)

Priority Applications (16)

Application Number Priority Date Filing Date Title
JP2011084762A JP5404685B2 (ja) 2011-04-06 2011-04-06 不揮発性半導体記憶装置
US13/246,004 US8385126B2 (en) 2011-04-06 2011-09-27 Nonvolatile semiconductor memory device
US13/749,029 US8649221B2 (en) 2011-04-06 2013-01-24 Nonvolatile semiconductor memory device
US14/088,744 US9025387B2 (en) 2011-04-06 2013-11-25 Nonvolatile semiconductor memory device
US14/677,111 US9472295B2 (en) 2011-04-06 2015-04-02 Nonvolatile semiconductor memory device
US15/263,518 US9691489B2 (en) 2011-04-06 2016-09-13 Nonvolatile semiconductor memory device with first and second read operations with different read voltages
US15/598,554 US9947415B2 (en) 2011-04-06 2017-05-18 Nonvolatile semiconductor memory device having a control circuit that controls voltage applied to non-selected word lines connected to unselected memory cells
US15/915,129 US10186321B2 (en) 2011-04-06 2018-03-08 Nonvolatile semiconductor memory device
US16/209,520 US10490286B2 (en) 2011-04-06 2018-12-04 Electrically-rewritable nonvolatile semiconductor memory device
US16/597,242 US10818362B2 (en) 2011-04-06 2019-10-09 Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage
US17/026,904 US11004520B2 (en) 2011-04-06 2020-09-21 Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage
US17/219,003 US11621041B2 (en) 2011-04-06 2021-03-31 Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage
US18/173,211 US11817155B2 (en) 2011-04-06 2023-02-23 Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage
US18/467,793 US12068040B2 (en) 2011-04-06 2023-09-15 Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage
US18/752,870 US12322454B2 (en) 2011-04-06 2024-06-25 Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage
US19/196,186 US20250273276A1 (en) 2011-04-06 2025-05-01 Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011084762A JP5404685B2 (ja) 2011-04-06 2011-04-06 不揮発性半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2012221522A JP2012221522A (ja) 2012-11-12
JP2012221522A5 JP2012221522A5 (enExample) 2013-03-28
JP5404685B2 true JP5404685B2 (ja) 2014-02-05

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Family Applications (1)

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JP2011084762A Active JP5404685B2 (ja) 2011-04-06 2011-04-06 不揮発性半導体記憶装置

Country Status (2)

Country Link
US (15) US8385126B2 (enExample)
JP (1) JP5404685B2 (enExample)

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KR20130045495A (ko) * 2011-10-26 2013-05-06 에스케이하이닉스 주식회사 불휘발성 메모리 장치 및 그것의 읽기 방법
JP2013200932A (ja) * 2012-03-26 2013-10-03 Toshiba Corp 不揮発性半導体記憶装置
TWI494930B (zh) * 2012-05-03 2015-08-01 Macronix Int Co Ltd 記憶體裝置之數個操作
US9007842B2 (en) * 2013-03-12 2015-04-14 Seagate Technology Llc Retention detection and/or channel tracking policy in a flash memory based storage system
WO2015004714A1 (ja) 2013-07-08 2015-01-15 株式会社 東芝 半導体記憶装置
KR102065664B1 (ko) * 2013-08-09 2020-01-13 삼성전자 주식회사 메모리 장치의 열화 상태 추정 방법 및 이를 이용한 메모리 시스템에서의 웨어 레벨링 방법
TWI601152B (zh) * 2013-08-19 2017-10-01 Toshiba Memory Corp Semiconductor memory device
JP2015176612A (ja) 2014-03-13 2015-10-05 株式会社東芝 不揮発性半導体記憶装置
US9672102B2 (en) * 2014-06-25 2017-06-06 Intel Corporation NAND memory devices systems, and methods using pre-read error recovery protocols of upper and lower pages
KR20160011939A (ko) * 2014-07-23 2016-02-02 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
KR20160043579A (ko) * 2014-10-13 2016-04-22 삼성전자주식회사 반도체 장치의 사용시간 매니징 방법 및 그에 따른 사용시간 매니징 부를 구비한 반도체 장치
US9928138B2 (en) * 2015-02-17 2018-03-27 Toshiba Memory Corporation Memory system
WO2016203631A1 (ja) * 2015-06-19 2016-12-22 株式会社日立製作所 フラッシュメモリデバイス
JP2017054562A (ja) * 2015-09-08 2017-03-16 株式会社東芝 半導体記憶装置
JP6581019B2 (ja) 2016-03-02 2019-09-25 東芝メモリ株式会社 半導体記憶装置
US9711231B1 (en) * 2016-06-24 2017-07-18 Sandisk Technologies Llc System solution for first read issue using time dependent read voltages
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US10262743B2 (en) 2016-10-25 2019-04-16 Sandisk Technologies Llc Command sequence for first read solution for memory
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CN109215716B (zh) * 2017-07-05 2021-01-19 北京兆易创新科技股份有限公司 提高nand型浮栅存储器可靠性的方法及装置
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US10726926B2 (en) * 2018-09-29 2020-07-28 Sandisk Technologies Llp Hot-cold VTH mismatch using VREAD modulation
CN111444038B (zh) * 2020-03-28 2021-08-10 华中科技大学 闪存存储器可靠性的实时检测方法、检测设备及存储系统
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Also Published As

Publication number Publication date
US20200043558A1 (en) 2020-02-06
JP2012221522A (ja) 2012-11-12
US20150213903A1 (en) 2015-07-30
US8649221B2 (en) 2014-02-11
US20190108885A1 (en) 2019-04-11
US9947415B2 (en) 2018-04-17
US9691489B2 (en) 2017-06-27
US20160379717A1 (en) 2016-12-29
US20120257453A1 (en) 2012-10-11
US20240005999A1 (en) 2024-01-04
US10818362B2 (en) 2020-10-27
US11817155B2 (en) 2023-11-14
US12322454B2 (en) 2025-06-03
US9025387B2 (en) 2015-05-05
US20210217481A1 (en) 2021-07-15
US20180197616A1 (en) 2018-07-12
US20170256321A1 (en) 2017-09-07
US8385126B2 (en) 2013-02-26
US11004520B2 (en) 2021-05-11
US20210005270A1 (en) 2021-01-07
US12068040B2 (en) 2024-08-20
US20240347113A1 (en) 2024-10-17
US20140085988A1 (en) 2014-03-27
US20130135939A1 (en) 2013-05-30
US20230197167A1 (en) 2023-06-22
US10186321B2 (en) 2019-01-22
US9472295B2 (en) 2016-10-18
US11621041B2 (en) 2023-04-04
US10490286B2 (en) 2019-11-26
US20250273276A1 (en) 2025-08-28

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