JP5367616B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

Info

Publication number
JP5367616B2
JP5367616B2 JP2010032040A JP2010032040A JP5367616B2 JP 5367616 B2 JP5367616 B2 JP 5367616B2 JP 2010032040 A JP2010032040 A JP 2010032040A JP 2010032040 A JP2010032040 A JP 2010032040A JP 5367616 B2 JP5367616 B2 JP 5367616B2
Authority
JP
Japan
Prior art keywords
silicon wafer
hole
silicon
substrate
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010032040A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010219513A5 (enExample
JP2010219513A (ja
Inventor
秀明 坂口
晶紀 白石
光敏 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010032040A priority Critical patent/JP5367616B2/ja
Priority to US12/709,838 priority patent/US8299370B2/en
Publication of JP2010219513A publication Critical patent/JP2010219513A/ja
Priority to US13/606,747 priority patent/US8777638B2/en
Publication of JP2010219513A5 publication Critical patent/JP2010219513A5/ja
Application granted granted Critical
Publication of JP5367616B2 publication Critical patent/JP5367616B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2010032040A 2009-02-23 2010-02-17 配線基板及びその製造方法 Active JP5367616B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010032040A JP5367616B2 (ja) 2009-02-23 2010-02-17 配線基板及びその製造方法
US12/709,838 US8299370B2 (en) 2009-02-23 2010-02-22 Wiring board and method of manufacturing the same
US13/606,747 US8777638B2 (en) 2009-02-23 2012-09-07 Wiring board and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009038932 2009-02-23
JP2009038932 2009-02-23
JP2010032040A JP5367616B2 (ja) 2009-02-23 2010-02-17 配線基板及びその製造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2013164899A Division JP5568169B2 (ja) 2009-02-23 2013-08-08 配線基板及びその製造方法
JP2013164900A Division JP5568170B2 (ja) 2009-02-23 2013-08-08 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2010219513A JP2010219513A (ja) 2010-09-30
JP2010219513A5 JP2010219513A5 (enExample) 2013-01-24
JP5367616B2 true JP5367616B2 (ja) 2013-12-11

Family

ID=42629961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010032040A Active JP5367616B2 (ja) 2009-02-23 2010-02-17 配線基板及びその製造方法

Country Status (2)

Country Link
US (2) US8299370B2 (enExample)
JP (1) JP5367616B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5636265B2 (ja) * 2010-11-15 2014-12-03 新光電気工業株式会社 半導体パッケージ及びその製造方法
KR101806806B1 (ko) * 2011-12-20 2017-12-11 삼성전자주식회사 전자 소자 탑재용 기판의 제조방법
JP2013168400A (ja) * 2012-02-14 2013-08-29 Tokyo Electron Ltd 半導体デバイス検査装置用配線基板及びその製造方法
JP6033130B2 (ja) * 2013-03-13 2016-11-30 新光電気工業株式会社 プローブガイド板及びその製造方法
JP6256741B2 (ja) * 2013-09-18 2018-01-10 日立化成株式会社 半導体素子搭載用パッケージ基板
EP3203509B1 (en) * 2016-02-04 2021-01-20 Services Pétroliers Schlumberger Double-sided hermetic multichip module
CN106057699B (zh) * 2016-07-20 2019-01-11 武汉华星光电技术有限公司 光阻层上过孔的测量方法
TW202142517A (zh) * 2020-05-12 2021-11-16 台灣愛司帝科技股份有限公司 基板拼接結構、基板拼接系統以及基板拼接方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5973396A (en) * 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
JP3796099B2 (ja) * 2000-05-12 2006-07-12 新光電気工業株式会社 半導体装置用インターポーザー、その製造方法および半導体装置
JP2002031650A (ja) 2000-07-18 2002-01-31 Ibiden Co Ltd プローブカード
JP3904484B2 (ja) * 2002-06-19 2007-04-11 新光電気工業株式会社 シリコン基板のスルーホールプラギング方法
FI119583B (fi) * 2003-02-26 2008-12-31 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
JP3800335B2 (ja) * 2003-04-16 2006-07-26 セイコーエプソン株式会社 光デバイス、光モジュール、半導体装置及び電子機器
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
JP4509869B2 (ja) * 2005-06-08 2010-07-21 新光電気工業株式会社 回路基板の製造方法
JP4698296B2 (ja) * 2005-06-17 2011-06-08 新光電気工業株式会社 貫通電極を有する半導体装置の製造方法
JP5064768B2 (ja) * 2006-11-22 2012-10-31 新光電気工業株式会社 電子部品および電子部品の製造方法
EP2144282A4 (en) * 2007-04-27 2010-06-09 Sumitomo Bakelite Co METHOD FOR BONDING SEMICONDUCTOR WAFERS AND METHOD FOR PRODUCING A SEMICONDUCTOR CONSTRUCTION ELEMENT
US8194411B2 (en) * 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules

Also Published As

Publication number Publication date
US8777638B2 (en) 2014-07-15
US8299370B2 (en) 2012-10-30
US20100212950A1 (en) 2010-08-26
JP2010219513A (ja) 2010-09-30
US20120325529A1 (en) 2012-12-27

Similar Documents

Publication Publication Date Title
TWI384630B (zh) 製造電子部件封裝結構之方法
JP5608605B2 (ja) 配線基板の製造方法
JP2010219513A (ja) 配線基板及びその製造方法
US7365007B2 (en) Interconnects with direct metalization and conductive polymer
CN106206409A (zh) 堆叠电子装置及其制造方法
JP5363384B2 (ja) 配線基板及びその製造方法
JP2012033973A (ja) 配線基板及び半導体パッケージ
JP2010034403A (ja) 配線基板及び電子部品装置
JP5568169B2 (ja) 配線基板及びその製造方法
JP2014236102A (ja) 貫通電極付き配線基板、その製造方法及び半導体装置
JP2010192696A (ja) 電子部品装置及びその製造方法
US10129980B2 (en) Circuit board and electronic component device
JP2004273480A (ja) 配線基板およびその製造方法および半導体装置
JP2011091185A (ja) 導電フィルムおよびその製造方法、並びに半導体装置およびその製造方法
JP4890959B2 (ja) 配線基板及びその製造方法並びに半導体パッケージ
KR100758188B1 (ko) 적층 기판, 그 제조 방법 및 그 적층 기판을 갖는 전자기기
JP4443349B2 (ja) 多層配線基板の製造方法
CN104157632B (zh) 基于选择性铝阳极氧化的bga基板多层互连结构及方法
JP2016157901A (ja) 電子装置
JP5836751B2 (ja) 薄膜配線基板
JP2011171531A (ja) 配線基板及びその製造方法
CN108305864B (zh) 端子
JP4593444B2 (ja) 電子部品実装構造体の製造方法
KR100601467B1 (ko) 소자를 실장한 인쇄회로기판 및 그 제조방법
JP2002151618A (ja) ビルドアッププリント配線板およびその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121129

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130621

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130702

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130808

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130903

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130911

R150 Certificate of patent or registration of utility model

Ref document number: 5367616

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150