JP5367413B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5367413B2 JP5367413B2 JP2009047841A JP2009047841A JP5367413B2 JP 5367413 B2 JP5367413 B2 JP 5367413B2 JP 2009047841 A JP2009047841 A JP 2009047841A JP 2009047841 A JP2009047841 A JP 2009047841A JP 5367413 B2 JP5367413 B2 JP 5367413B2
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
- H10N10/17—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L2924/153—Connection portion
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
14,104,204,304:半導体チップ、
100,200,300:半導体装置。
102,202,302:実装基板
104a,204a,304a:集積回路形成面
112N,212N,312N:N型半導体
112P,212P,312P:P型半導体
116,216,316:第1導体層
134,242,334:第2導体層
Claims (4)
- 第1の面と当該第1の面と反対の第2の面とを有するシリコンインターポーザと;
前記シリコンインターポーザの第1の面側に搭載された複数の半導体チップとを備え、
前記シリコンインターポーザには、前記第1及び第2の面に渡る複数の貫通孔が設けられ、
前記貫通孔には、ペルチェ素子を構成するN型半導体及びP型半導体が各々形成され、
前記半導体チップと前記N型半導体及びP型半導体との間に配置された第1の導体層と;前記シリコンインターポーザの前記第2の面に形成され、前記N型半導体及びP型半導体と導通する外部電極とを更に備えたことを特徴とする半導体装置。 - 前記N型半導体及びP型半導体と前記外部電極との間に形成された第2の導体層を更に備えたことを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップを封止する封止樹脂層を更に備え、
前記封止樹脂には、前記第1の導体層と導通する貫通電極が形成され、
前記貫通電極が外部端子を介して実装基板に導通し、
前記第2の導体層が外部に対して露出することを特徴とする請求項2に記載の半導体装置。 - 前記半導体チップの発熱部が吸熱作用を生じる再配線層によって被覆され、
前記再配線層は、前記第1の導体層に導通していることを特徴とする請求項1乃至3の何れか一項に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009047841A JP5367413B2 (ja) | 2009-03-02 | 2009-03-02 | 半導体装置 |
US12/659,209 US8319331B2 (en) | 2009-03-02 | 2010-03-01 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009047841A JP5367413B2 (ja) | 2009-03-02 | 2009-03-02 | 半導体装置 |
Publications (2)
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JP2010205818A JP2010205818A (ja) | 2010-09-16 |
JP5367413B2 true JP5367413B2 (ja) | 2013-12-11 |
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JP2009047841A Active JP5367413B2 (ja) | 2009-03-02 | 2009-03-02 | 半導体装置 |
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US (1) | US8319331B2 (ja) |
JP (1) | JP5367413B2 (ja) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5347886B2 (ja) * | 2009-10-05 | 2013-11-20 | 日本電気株式会社 | 3次元半導体装置および3次元半導体装置の冷却方法 |
DE102010029526B4 (de) * | 2010-05-31 | 2012-05-24 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Halbleiterbauelement mit einer gestapelten Chipkonfiguration mit einem integrierten Peltier-Element |
CN101930954B (zh) * | 2010-08-23 | 2012-02-15 | 北京大学 | 一种soi场效应晶体管的散热结构 |
US8803269B2 (en) * | 2011-05-05 | 2014-08-12 | Cisco Technology, Inc. | Wafer scale packaging platform for transceivers |
FR2977976A1 (fr) * | 2011-07-13 | 2013-01-18 | St Microelectronics Rousset | Procede de generation d'energie electrique au sein d'une structure integree tridimensionnelle, et dispositif de liaison correspondant |
US8604867B2 (en) * | 2011-11-28 | 2013-12-10 | Qualcomm Incorporated | Energy harvesting in integrated circuit packages |
US20130233598A1 (en) * | 2012-03-08 | 2013-09-12 | International Business Machines Corporation | Flexible film carrier to increase interconnect density of modules and methods thereof |
JP2014066527A (ja) * | 2012-09-24 | 2014-04-17 | National Institute Of Advanced Industrial & Technology | 積層lsiの接続状態の検査方法 |
FR3000300B1 (fr) | 2012-12-26 | 2015-02-27 | Commissariat Energie Atomique | Circuit integre et procede de fabrication d'un circuit equipe d'une sonde de temperature |
BR112016001796A2 (pt) * | 2013-07-30 | 2017-08-01 | Harman Becker Automotive Systems Gmbh | módulo eletrônico |
US9099427B2 (en) * | 2013-10-30 | 2015-08-04 | International Business Machines Corporation | Thermal energy dissipation using backside thermoelectric devices |
KR102297283B1 (ko) * | 2014-06-23 | 2021-09-03 | 삼성전기주식회사 | 열전 모듈을 갖는 기판 및 이를 이용한 반도체 패키지 |
RU2584575C1 (ru) * | 2014-12-25 | 2016-05-20 | Общество с ограниченной ответственностью "ЗЕЛНАС" | Интерпозер и способ его изготовления |
US9913405B2 (en) | 2015-03-25 | 2018-03-06 | Globalfoundries Inc. | Glass interposer with embedded thermoelectric devices |
US9559283B2 (en) | 2015-03-30 | 2017-01-31 | International Business Machines Corporation | Integrated circuit cooling using embedded peltier micro-vias in substrate |
US9941458B2 (en) | 2015-03-30 | 2018-04-10 | International Business Machines Corporation | Integrated circuit cooling using embedded peltier micro-vias in substrate |
US11177317B2 (en) | 2016-04-04 | 2021-11-16 | Synopsys, Inc. | Power harvesting for integrated circuits |
US9773717B1 (en) | 2016-08-22 | 2017-09-26 | Globalfoundries Inc. | Integrated circuits with peltier cooling provided by back-end wiring |
US20180108642A1 (en) * | 2016-10-13 | 2018-04-19 | Globalfoundries Inc. | Interposer heater for high bandwidth memory applications |
US20200119250A1 (en) * | 2018-10-11 | 2020-04-16 | Intel Corporation | In-situ formation of a thermoelectric device in a substrate packaging |
WO2023276559A1 (ja) * | 2021-06-30 | 2023-01-05 | リンテック株式会社 | 半導体封止体 |
WO2023176522A1 (ja) * | 2022-03-15 | 2023-09-21 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
CN117177431A (zh) * | 2022-05-25 | 2023-12-05 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制备方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3521521B2 (ja) * | 1994-06-20 | 2004-04-19 | ヤマハ株式会社 | 半導体装置の製造方法 |
JP2958451B1 (ja) * | 1998-03-05 | 1999-10-06 | 工業技術院長 | 熱電変換材料及びその製造方法 |
US6586835B1 (en) * | 1998-08-31 | 2003-07-01 | Micron Technology, Inc. | Compact system module with built-in thermoelectric cooling |
JP2004228485A (ja) | 2003-01-27 | 2004-08-12 | Hitachi Ltd | 半導体チップ積層パッケージ構造、及び、かかるパッケージ構造に好適な半導体装置 |
JP4485865B2 (ja) * | 2004-07-13 | 2010-06-23 | Okiセミコンダクタ株式会社 | 半導体装置、及びその製造方法 |
JP4581768B2 (ja) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | 半導体装置の製造方法 |
US7405146B2 (en) * | 2006-01-24 | 2008-07-29 | Kinsus Interconnect Technology Corp. | Electroplating method by transmitting electric current from a ball side |
JP2008153393A (ja) * | 2006-12-15 | 2008-07-03 | Sharp Corp | Icチップ実装パッケージ |
JP2008198928A (ja) * | 2007-02-15 | 2008-08-28 | Sony Corp | 冷却構造及びこの構造を内蔵した電子機器 |
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2009
- 2009-03-02 JP JP2009047841A patent/JP5367413B2/ja active Active
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2010
- 2010-03-01 US US12/659,209 patent/US8319331B2/en active Active
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JP2010205818A (ja) | 2010-09-16 |
US8319331B2 (en) | 2012-11-27 |
US20100219525A1 (en) | 2010-09-02 |
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