JP5366517B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5366517B2
JP5366517B2 JP2008303618A JP2008303618A JP5366517B2 JP 5366517 B2 JP5366517 B2 JP 5366517B2 JP 2008303618 A JP2008303618 A JP 2008303618A JP 2008303618 A JP2008303618 A JP 2008303618A JP 5366517 B2 JP5366517 B2 JP 5366517B2
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Prior art keywords
layer
single crystal
substrate
inorganic insulating
insulating film
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Expired - Fee Related
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JP2008303618A
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Japanese (ja)
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JP2009158939A5 (enExample
JP2009158939A (ja
Inventor
薫 土屋
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008303618A priority Critical patent/JP5366517B2/ja
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Publication of JP2009158939A5 publication Critical patent/JP2009158939A5/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0214Manufacture or treatment of multiple TFTs using temporary substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • H10D88/01Manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9202Forming additional connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes

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  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Recrystallisation Techniques (AREA)
  • Dram (AREA)
JP2008303618A 2007-12-03 2008-11-28 半導体装置の作製方法 Expired - Fee Related JP5366517B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008303618A JP5366517B2 (ja) 2007-12-03 2008-11-28 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007311910 2007-12-03
JP2007311910 2007-12-03
JP2008303618A JP5366517B2 (ja) 2007-12-03 2008-11-28 半導体装置の作製方法

Publications (3)

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JP2009158939A JP2009158939A (ja) 2009-07-16
JP2009158939A5 JP2009158939A5 (enExample) 2011-10-27
JP5366517B2 true JP5366517B2 (ja) 2013-12-11

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JP (1) JP5366517B2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200047898A (ko) * 2018-10-26 2020-05-08 삼성디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시 장치
US11257886B2 (en) 2018-10-05 2022-02-22 Samsung Display Co., Ltd. Organic light emitting diode display

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007023284A1 (en) * 2005-08-24 2007-03-01 Fry's Metals Inc. Reducing joint embrittlement in lead-free soldering processes
US8284557B2 (en) * 2007-10-18 2012-10-09 Kyocera Corporation Circuit board, mounting structure, and method for manufacturing circuit board
US20090193676A1 (en) * 2008-01-31 2009-08-06 Guo Shengguang Shoe Drying Apparatus
JP5240437B2 (ja) * 2008-04-24 2013-07-17 信越半導体株式会社 多層シリコン半導体ウェーハの作製方法
JP5240651B2 (ja) * 2008-04-30 2013-07-17 信越半導体株式会社 多層シリコン半導体ウェーハ及びその作製方法
JP5358324B2 (ja) 2008-07-10 2013-12-04 株式会社半導体エネルギー研究所 電子ペーパー
US20100184241A1 (en) * 2009-01-16 2010-07-22 Edison Opto Corporation Method for manufacturing thin type light emitting diode assembly
KR20220153647A (ko) 2009-10-29 2022-11-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR101669476B1 (ko) * 2009-10-30 2016-10-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 논리 회로 및 반도체 장치
KR20250075719A (ko) * 2009-10-30 2025-05-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
WO2011070900A1 (en) 2009-12-08 2011-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
WO2011070892A1 (en) 2009-12-08 2011-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR101813460B1 (ko) * 2009-12-18 2017-12-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR102088281B1 (ko) * 2010-01-22 2020-03-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
WO2011096271A1 (en) * 2010-02-05 2011-08-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
KR101822962B1 (ko) 2010-02-05 2018-01-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR101838130B1 (ko) * 2010-02-12 2018-03-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작방법
CN106449649B (zh) 2010-03-08 2019-09-27 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法
CN102822978B (zh) 2010-03-12 2015-07-22 株式会社半导体能源研究所 半导体装置及其制造方法
WO2011152254A1 (en) 2010-06-04 2011-12-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2011152233A1 (en) * 2010-06-04 2011-12-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2011152286A1 (en) * 2010-06-04 2011-12-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2012002186A1 (en) 2010-07-02 2012-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN103003934B (zh) * 2010-07-16 2015-07-01 株式会社半导体能源研究所 半导体器件
JP2013009285A (ja) * 2010-08-26 2013-01-10 Semiconductor Energy Lab Co Ltd 信号処理回路及びその駆動方法
WO2012029638A1 (en) 2010-09-03 2012-03-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2012256821A (ja) * 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
TWI539453B (zh) * 2010-09-14 2016-06-21 半導體能源研究所股份有限公司 記憶體裝置和半導體裝置
KR20120042151A (ko) * 2010-10-22 2012-05-03 삼성모바일디스플레이주식회사 플렉서블 디스플레이 장치의 제조 방법
WO2012060253A1 (en) * 2010-11-05 2012-05-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
EP2466426A1 (en) * 2010-12-16 2012-06-20 Innovation & Infinity Global Corp. Diffusion barrier structure, transparent conductive structure and method for making the same
US9601178B2 (en) 2011-01-26 2017-03-21 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device
JP6023453B2 (ja) * 2011-04-15 2016-11-09 株式会社半導体エネルギー研究所 記憶装置
US9935622B2 (en) * 2011-04-28 2018-04-03 Semiconductor Energy Laboratory Co., Ltd. Comparator and semiconductor device including comparator
CN103022012B (zh) 2011-09-21 2017-03-01 株式会社半导体能源研究所 半导体存储装置
US8981367B2 (en) 2011-12-01 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6081171B2 (ja) 2011-12-09 2017-02-15 株式会社半導体エネルギー研究所 記憶装置
JP6105266B2 (ja) 2011-12-15 2017-03-29 株式会社半導体エネルギー研究所 記憶装置
JP6134515B2 (ja) * 2012-01-17 2017-05-24 株式会社半導体エネルギー研究所 記憶装置
US9886794B2 (en) 2012-06-05 2018-02-06 Apple Inc. Problem reporting in maps
JP5960000B2 (ja) * 2012-09-05 2016-08-02 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US9165623B2 (en) * 2013-10-13 2015-10-20 Taiwan Semiconductor Manufacturing Company Limited Memory arrangement
US9443758B2 (en) 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
JP6580863B2 (ja) 2014-05-22 2019-09-25 株式会社半導体エネルギー研究所 半導体装置、健康管理システム
JP6751385B2 (ja) * 2014-07-08 2020-09-02 マサチューセッツ インスティテュート オブ テクノロジー 基板の製造方法
KR101658716B1 (ko) * 2014-12-31 2016-09-30 엘지디스플레이 주식회사 표시 장치
US9343499B1 (en) * 2015-04-23 2016-05-17 Omnivision Technologies, Inc. Integrated circuit stack with strengthened wafer bonding
JP2016225614A (ja) 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置
US9773787B2 (en) 2015-11-03 2017-09-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, memory device, electronic device, or method for driving the semiconductor device
CN105470205B (zh) * 2015-12-24 2018-09-07 上海天马有机发光显示技术有限公司 一种多层低温多晶硅薄膜晶体管(ltps-tft)制造方法
US10090193B1 (en) * 2017-11-16 2018-10-02 Globalfoundries Inc. Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method
US10192819B1 (en) 2017-11-16 2019-01-29 Globalfoundries Inc. Integrated circuit structure incorporating stacked field effect transistors
US10304832B1 (en) 2017-11-16 2019-05-28 Globalfoundries Inc. Integrated circuit structure incorporating stacked field effect transistors and method
CN111937490B (zh) 2018-04-20 2023-07-18 堺显示器制品株式会社 有机el装置及其制造方法
CN109557042B (zh) * 2018-11-26 2021-10-08 广东朗研科技有限公司 基于半导体镀纳米介孔金属薄膜结构及太赫兹波增强系统
US11239238B2 (en) 2019-10-29 2022-02-01 Intel Corporation Thin film transistor based memory cells on both sides of a layer of logic devices
US11817442B2 (en) 2020-12-08 2023-11-14 Intel Corporation Hybrid manufacturing for integrated circuit devices and assemblies
US11756886B2 (en) 2020-12-08 2023-09-12 Intel Corporation Hybrid manufacturing of microeletronic assemblies with first and second integrated circuit structures
US12412835B2 (en) 2021-04-27 2025-09-09 Intel Corporation Back-side power delivery with glass support at the front
US20220406754A1 (en) * 2021-06-17 2022-12-22 Intel Corporation Layer transfer on non-semiconductor support structures
US12463102B2 (en) * 2022-05-11 2025-11-04 Xintec Inc. Semiconductor device structure and method for forming the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2742747B2 (ja) 1992-05-29 1998-04-22 株式会社半導体エネルギー研究所 薄膜トランジスタを有する多層半導体集積回路
JPH10223495A (ja) * 1997-02-04 1998-08-21 Nippon Telegr & Teleph Corp <Ntt> 柔軟な構造を有する半導体装置とその製造方法
US6525415B2 (en) * 1999-12-28 2003-02-25 Fuji Xerox Co., Ltd. Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor
JP4137328B2 (ja) 1999-12-28 2008-08-20 光正 小柳 3次元半導体集積回路装置の製造方法
SG143972A1 (en) * 2000-09-14 2008-07-29 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
JP4027740B2 (ja) * 2001-07-16 2007-12-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4554152B2 (ja) * 2002-12-19 2010-09-29 株式会社半導体エネルギー研究所 半導体チップの作製方法
US6821826B1 (en) * 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
US7084045B2 (en) * 2003-12-12 2006-08-01 Seminconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
JP4538254B2 (ja) * 2004-03-25 2010-09-08 ルネサスエレクトロニクス株式会社 Euvリソグラフィー用マスク基板及びその製造方法
JP5446059B2 (ja) * 2006-04-24 2014-03-19 豊田合成株式会社 GaN系半導体発光素子の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11257886B2 (en) 2018-10-05 2022-02-22 Samsung Display Co., Ltd. Organic light emitting diode display
US11856818B2 (en) 2018-10-05 2023-12-26 Samsung Display Co., Ltd. Organic light emitting diode display
KR20200047898A (ko) * 2018-10-26 2020-05-08 삼성디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시 장치
US10991783B2 (en) 2018-10-26 2021-04-27 Samsung Display Co., Ltd. Scan driver and display device including the same
KR102779433B1 (ko) 2018-10-26 2025-03-12 삼성디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시 장치

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US7696063B2 (en) 2010-04-13
US20090142888A1 (en) 2009-06-04
JP2009158939A (ja) 2009-07-16

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