JP5363377B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP5363377B2
JP5363377B2 JP2010034314A JP2010034314A JP5363377B2 JP 5363377 B2 JP5363377 B2 JP 5363377B2 JP 2010034314 A JP2010034314 A JP 2010034314A JP 2010034314 A JP2010034314 A JP 2010034314A JP 5363377 B2 JP5363377 B2 JP 5363377B2
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JP
Japan
Prior art keywords
wiring board
aluminum oxide
layer
wiring
oxide substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010034314A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011171531A (ja
JP2011171531A5 (OSRAM
Inventor
道夫 堀内
昌樹 真田
純廣 市川
安衛 徳武
勇一 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010034314A priority Critical patent/JP5363377B2/ja
Publication of JP2011171531A publication Critical patent/JP2011171531A/ja
Publication of JP2011171531A5 publication Critical patent/JP2011171531A5/ja
Application granted granted Critical
Publication of JP5363377B2 publication Critical patent/JP5363377B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP2010034314A 2010-02-19 2010-02-19 配線基板及びその製造方法 Expired - Fee Related JP5363377B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010034314A JP5363377B2 (ja) 2010-02-19 2010-02-19 配線基板及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010034314A JP5363377B2 (ja) 2010-02-19 2010-02-19 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2011171531A JP2011171531A (ja) 2011-09-01
JP2011171531A5 JP2011171531A5 (OSRAM) 2013-01-24
JP5363377B2 true JP5363377B2 (ja) 2013-12-11

Family

ID=44685332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010034314A Expired - Fee Related JP5363377B2 (ja) 2010-02-19 2010-02-19 配線基板及びその製造方法

Country Status (1)

Country Link
JP (1) JP5363377B2 (OSRAM)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6282425B2 (ja) * 2012-10-29 2018-02-21 新光電気工業株式会社 配線基板の製造方法
JP6375249B2 (ja) 2015-03-02 2018-08-15 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
CN116057681A (zh) * 2020-08-12 2023-05-02 富士胶片株式会社 结构体、结构体的制造方法、接合体的制造方法及器件的制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3154713B2 (ja) * 1990-03-16 2001-04-09 株式会社リコー 異方性導電膜およびその製造方法
JPH05291721A (ja) * 1992-04-10 1993-11-05 Cmk Corp プリント配線板
JPH06287774A (ja) * 1993-04-05 1994-10-11 Metsuku Kk 銅および銅合金の表面処理剤
JP3130707B2 (ja) * 1993-08-09 2001-01-31 株式会社日立製作所 プリント基板およびその製造方法
JP3087152B2 (ja) * 1993-09-08 2000-09-11 富士通株式会社 樹脂フィルム多層回路基板の製造方法
JPH09266374A (ja) * 1996-03-28 1997-10-07 Chichibu Onoda Cement Corp 放熱性基板の製造方法
JP3736046B2 (ja) * 1997-06-19 2006-01-18 株式会社トッパンＮｅｃサーキットソリューションズ 半導体装置用基板及びその製造方法
JP4558883B2 (ja) * 2000-03-24 2010-10-06 義和 小林 酸性無電解錫めっき液中の銅の定量方法
JP2004273480A (ja) * 2003-03-05 2004-09-30 Sony Corp 配線基板およびその製造方法および半導体装置
JP2009099831A (ja) * 2007-10-18 2009-05-07 Nippon Circuit Kogyo Kk 配線基板の製造方法
JP5344667B2 (ja) * 2007-12-18 2013-11-20 太陽誘電株式会社 回路基板およびその製造方法並びに回路モジュール

Also Published As

Publication number Publication date
JP2011171531A (ja) 2011-09-01

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