JP5335237B2 - 深さ方向に分離層を含む多層構造物の製造方法 - Google Patents

深さ方向に分離層を含む多層構造物の製造方法 Download PDF

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JP5335237B2
JP5335237B2 JP2007513998A JP2007513998A JP5335237B2 JP 5335237 B2 JP5335237 B2 JP 5335237B2 JP 2007513998 A JP2007513998 A JP 2007513998A JP 2007513998 A JP2007513998 A JP 2007513998A JP 5335237 B2 JP5335237 B2 JP 5335237B2
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layer
intermediate layer
absorption
material constituting
multilayer structure
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JP2008501228A (ja
JP2008501228A5 (enExample
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ミッシェル ブリュエル
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エス．オー．アイ．テック シリコン オン インシュレイター テクノロジーズ
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    • H10P90/1916—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H10P34/42—
    • H10W10/181—

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Or Chemical Processes And Apparatus (AREA)
JP2007513998A 2004-06-01 2005-05-20 深さ方向に分離層を含む多層構造物の製造方法 Expired - Lifetime JP5335237B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0405883A FR2870988B1 (fr) 2004-06-01 2004-06-01 Procede de realisation d'une structure multi-couches comportant, en profondeur, une couche de separation
FR0405883 2004-06-01
PCT/FR2005/001262 WO2006000669A2 (fr) 2004-06-01 2005-05-20 Procédé de réalisation d'une structure multi-couches comportant, en profondeur, une couche de séparation.

Publications (3)

Publication Number Publication Date
JP2008501228A JP2008501228A (ja) 2008-01-17
JP2008501228A5 JP2008501228A5 (enExample) 2012-11-01
JP5335237B2 true JP5335237B2 (ja) 2013-11-06

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JP2007513998A Expired - Lifetime JP5335237B2 (ja) 2004-06-01 2005-05-20 深さ方向に分離層を含む多層構造物の製造方法

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US (1) US7846816B2 (enExample)
EP (1) EP1774579B1 (enExample)
JP (1) JP5335237B2 (enExample)
CN (1) CN100444335C (enExample)
AU (1) AU2005256723B8 (enExample)
BR (1) BRPI0511207A (enExample)
FR (1) FR2870988B1 (enExample)
WO (1) WO2006000669A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8288684B2 (en) * 2007-05-03 2012-10-16 Electro Scientific Industries, Inc. Laser micro-machining system with post-scan lens deflection
FR2961719B1 (fr) * 2010-06-24 2013-09-27 Soitec Silicon On Insulator Procede de traitement d'une piece en un materiau compose
FR2965396B1 (fr) * 2010-09-29 2013-02-22 S O I Tec Silicon On Insulator Tech Substrat démontable, procédés de fabrication et de démontage d'un tel substrat
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur
FR2980279B1 (fr) 2011-09-20 2013-10-11 Soitec Silicon On Insulator Procede de fabrication d'une structure composite a separer par exfoliation
WO2013147202A1 (ja) * 2012-03-30 2013-10-03 帝人株式会社 半導体積層体及びその製造方法、半導体デバイスの製造方法、半導体デバイス、ドーパント組成物、ドーパント注入層、並びにドープ層の形成方法
FR2991499A1 (fr) * 2012-05-31 2013-12-06 Commissariat Energie Atomique Procede et systeme d'obtention d'une tranche semi-conductrice
CN106340439A (zh) * 2015-07-06 2017-01-18 勤友光电股份有限公司 用于镭射剥离处理的晶圆结构
DE102016000051A1 (de) 2016-01-05 2017-07-06 Siltectra Gmbh Verfahren und Vorrichtung zum planaren Erzeugen von Modifikationen in Festkörpern
CN108883502B (zh) * 2016-03-22 2022-04-15 西尔特克特拉有限责任公司 待分裂固体的组合的激光处理
US10978311B2 (en) 2016-12-12 2021-04-13 Siltectra Gmbh Method for thinning solid body layers provided with components
TWI631022B (zh) * 2016-12-26 2018-08-01 謙華科技股份有限公司 熱印頭模組之製造方法
FR3079657B1 (fr) 2018-03-29 2024-03-15 Soitec Silicon On Insulator Structure composite demontable par application d'un flux lumineux, et procede de separation d'une telle structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2506344B2 (fr) * 1980-02-01 1986-07-11 Commissariat Energie Atomique Procede de dopage de semi-conducteurs
US4415373A (en) * 1981-11-17 1983-11-15 Allied Corporation Laser process for gettering defects in semiconductor devices
JP2004140380A (ja) * 1996-08-27 2004-05-13 Seiko Epson Corp 薄膜デバイスの転写方法、及びデバイスの製造方法
EP1655633A3 (en) * 1996-08-27 2006-06-21 Seiko Epson Corporation Exfoliating method, transferring method of thin film device, thin film integrated circuit device, and liquid crystal display device
JPH1126733A (ja) 1997-07-03 1999-01-29 Seiko Epson Corp 薄膜デバイスの転写方法、薄膜デバイス、薄膜集積回路装置，アクティブマトリクス基板、液晶表示装置および電子機器
EP0926709A3 (en) * 1997-12-26 2000-08-30 Canon Kabushiki Kaisha Method of manufacturing an SOI structure
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP3911929B2 (ja) * 1999-10-25 2007-05-09 セイコーエプソン株式会社 液晶表示装置の製造方法
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
US7211214B2 (en) * 2000-07-18 2007-05-01 Princeton University Laser assisted direct imprint lithography
AU2002348835A1 (en) 2001-11-30 2003-06-10 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device
US6555439B1 (en) * 2001-12-18 2003-04-29 Advanced Micro Devices, Inc. Partial recrystallization of source/drain region before laser thermal annealing
US7105425B1 (en) * 2002-05-16 2006-09-12 Advanced Micro Devices, Inc. Single electron devices formed by laser thermal annealing

Also Published As

Publication number Publication date
AU2005256723B2 (en) 2011-02-10
JP2008501228A (ja) 2008-01-17
AU2005256723B8 (en) 2011-07-28
US7846816B2 (en) 2010-12-07
EP1774579B1 (fr) 2012-05-16
WO2006000669A2 (fr) 2006-01-05
FR2870988B1 (fr) 2006-08-11
EP1774579A2 (fr) 2007-04-18
FR2870988A1 (fr) 2005-12-02
CN100444335C (zh) 2008-12-17
BRPI0511207A (pt) 2007-11-27
CN1998071A (zh) 2007-07-11
AU2005256723A1 (en) 2006-01-05
WO2006000669A3 (fr) 2007-01-25
US20090053877A1 (en) 2009-02-26

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