JP5300158B2 - 成形密着性を向上させたパッケージ化電子デバイス用リードフレーム - Google Patents

成形密着性を向上させたパッケージ化電子デバイス用リードフレーム Download PDF

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Publication number
JP5300158B2
JP5300158B2 JP2011504022A JP2011504022A JP5300158B2 JP 5300158 B2 JP5300158 B2 JP 5300158B2 JP 2011504022 A JP2011504022 A JP 2011504022A JP 2011504022 A JP2011504022 A JP 2011504022A JP 5300158 B2 JP5300158 B2 JP 5300158B2
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Japan
Prior art keywords
die pad
group
lead frame
lead
extends
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JP2011504022A
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English (en)
Japanese (ja)
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JP2011517113A (ja
JP2011517113A5 (enExample
Inventor
アール． フーパー、スティーブン
ディ． マクドナルド、ジェームズ
エス． シャムウェイ、ラッセル
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NXP USA Inc
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NXP USA Inc
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Publication of JP2011517113A publication Critical patent/JP2011517113A/ja
Publication of JP2011517113A5 publication Critical patent/JP2011517113A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2011504022A 2008-04-08 2009-02-13 成形密着性を向上させたパッケージ化電子デバイス用リードフレーム Active JP5300158B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/099,446 US7834431B2 (en) 2008-04-08 2008-04-08 Leadframe for packaged electronic device with enhanced mold locking capability
US12/099,446 2008-04-08
PCT/US2009/034073 WO2009126367A1 (en) 2008-04-08 2009-02-13 Leadframe for packaged electronic device with enhanced mold locking capability

Publications (3)

Publication Number Publication Date
JP2011517113A JP2011517113A (ja) 2011-05-26
JP2011517113A5 JP2011517113A5 (enExample) 2012-03-29
JP5300158B2 true JP5300158B2 (ja) 2013-09-25

Family

ID=41132492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011504022A Active JP5300158B2 (ja) 2008-04-08 2009-02-13 成形密着性を向上させたパッケージ化電子デバイス用リードフレーム

Country Status (4)

Country Link
US (1) US7834431B2 (enExample)
JP (1) JP5300158B2 (enExample)
TW (1) TW200945531A (enExample)
WO (1) WO2009126367A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115285B2 (en) * 2008-03-14 2012-02-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
CN102522375B (zh) * 2008-07-30 2015-04-08 三洋电机株式会社 半导体装置、半导体装置的制造方法及引线框
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
CN101882609A (zh) * 2009-05-08 2010-11-10 飞思卡尔半导体公司 用于半导体封装体的引线框
US8742555B2 (en) 2011-08-30 2014-06-03 Jian Wen Lead frame having a flag with in-plane and out-of-plane mold locking features
JP5817513B2 (ja) * 2011-12-27 2015-11-18 大日本印刷株式会社 半導体装置製造用リードフレーム及び半導体装置の製造方法
US9013028B2 (en) * 2013-01-04 2015-04-21 Texas Instruments Incorporated Integrated circuit package and method of making
US9515009B2 (en) 2015-01-08 2016-12-06 Texas Instruments Incorporated Packaged semiconductor device having leadframe features preventing delamination
CN106129035B (zh) 2015-05-05 2021-01-29 恩智浦美国有限公司 具有模制锁定的露出焊盘式集成电路封装件
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP6430422B2 (ja) 2016-02-29 2018-11-28 株式会社東芝 半導体装置
US10998255B2 (en) 2018-07-12 2021-05-04 Nxp Usa, Inc. Overmolded microelectronic packages containing knurled flanges and methods for the production thereof
US11901309B2 (en) 2019-11-12 2024-02-13 Semiconductor Components Industries, Llc Semiconductor device package assemblies with direct leadframe attachment
TWI784474B (zh) * 2021-04-12 2022-11-21 順德工業股份有限公司 導線架料片及其導線架
JP2022190980A (ja) 2021-06-15 2022-12-27 富士電機株式会社 半導体装置
US20230031682A1 (en) * 2021-07-28 2023-02-02 Stmicroelectronics S.R.L. Method of manufacturing substrates for semiconductor devices, corresponding substrate and semiconductor device
IT202100021638A1 (it) 2021-08-10 2023-02-10 St Microelectronics Srl Procedimento per fabbricare dispositivi a semiconduttore, dispositivo a semiconduttore e assortimento di dispositivi a semiconduttore corrispondenti
CN115360192A (zh) * 2022-09-15 2022-11-18 华天科技（西安）有限公司 一种通信射频产品引线框架的结构及其制备方法
WO2024247688A1 (ja) * 2023-06-02 2024-12-05 ローム株式会社 半導体装置および車両

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5126820A (en) * 1985-02-01 1992-06-30 Advanced Micro Devices, Inc. Thermal expansion compensated metal lead frame for integrated circuit package
JPH0685132A (ja) * 1992-09-07 1994-03-25 Mitsubishi Electric Corp 半導体装置
JPH08172145A (ja) * 1994-12-16 1996-07-02 Texas Instr Japan Ltd 半導体装置及び放熱性部品
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
JP2000269401A (ja) * 1999-03-16 2000-09-29 Toshiba Microelectronics Corp 半導体装置
KR100335480B1 (ko) * 1999-08-24 2002-05-04 김덕중 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지
US6847103B1 (en) * 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
JP3706533B2 (ja) * 2000-09-20 2005-10-12 三洋電機株式会社 半導体装置および半導体モジュール
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
US7091602B2 (en) * 2002-12-13 2006-08-15 Freescale Semiconductor, Inc. Miniature moldlocks for heatsink or flag for an overmolded plastic package
US7217599B2 (en) * 2003-06-12 2007-05-15 St Assembly Test Services Ltd. Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor
US7049683B1 (en) * 2003-07-19 2006-05-23 Ns Electronics Bangkok (1993) Ltd. Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound
US6984878B2 (en) * 2004-05-24 2006-01-10 Advanced Semiconductor Engineering, Inc. Leadless leadframe with an improved die pad for mold locking
US20080079127A1 (en) * 2006-10-03 2008-04-03 Texas Instruments Incorporated Pin Array No Lead Package and Assembly Method Thereof

Also Published As

Publication number Publication date
TW200945531A (en) 2009-11-01
WO2009126367A1 (en) 2009-10-15
US20090250795A1 (en) 2009-10-08
JP2011517113A (ja) 2011-05-26
US7834431B2 (en) 2010-11-16

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