JP5294517B2 - アッド‐オン層形成方法 - Google Patents

アッド‐オン層形成方法 Download PDF

Info

Publication number
JP5294517B2
JP5294517B2 JP2011218346A JP2011218346A JP5294517B2 JP 5294517 B2 JP5294517 B2 JP 5294517B2 JP 2011218346 A JP2011218346 A JP 2011218346A JP 2011218346 A JP2011218346 A JP 2011218346A JP 5294517 B2 JP5294517 B2 JP 5294517B2
Authority
JP
Japan
Prior art keywords
layer
fld
soi
substrate
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2011218346A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012064950A (ja
Inventor
リー，サン−ユン
Original Assignee
リー，サン−ユン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by リー，サン−ユン filed Critical リー，サン−ユン
Publication of JP2012064950A publication Critical patent/JP2012064950A/ja
Application granted granted Critical
Publication of JP5294517B2 publication Critical patent/JP5294517B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Non-Volatile Memory (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
JP2011218346A 2003-06-24 2011-09-30 アッド‐オン層形成方法 Expired - Fee Related JP5294517B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20030040920 2003-06-24
KR10-2003-0040920 2003-06-24
KR10-2003-0047515 2003-07-12
KR1020030047515A KR100904771B1 (ko) 2003-06-24 2003-07-12 3차원 집적회로 구조 및 제작 방법

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2006517574A Division JP5202842B2 (ja) 2003-06-24 2004-06-23 三次元集積回路構造及びこれを作る方法

Publications (2)

Publication Number Publication Date
JP2012064950A JP2012064950A (ja) 2012-03-29
JP5294517B2 true JP5294517B2 (ja) 2013-09-18

Family

ID=36840981

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2011218346A Expired - Fee Related JP5294517B2 (ja) 2003-06-24 2011-09-30 アッド‐オン層形成方法
JP2012135533A Pending JP2012253358A (ja) 2003-06-24 2012-06-15 半導体構造

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2012135533A Pending JP2012253358A (ja) 2003-06-24 2012-06-15 半導体構造

Country Status (3)

Country Link
JP (2) JP5294517B2 (ko)
KR (1) KR100904771B1 (ko)
CN (1) CN1809914B (ko)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100989546B1 (ko) * 2008-05-21 2010-10-25 이상윤 3차원 반도체 장치의 제조 방법
KR100975332B1 (ko) * 2008-05-30 2010-08-12 이상윤 반도체 장치 및 그 제조 방법
KR100791071B1 (ko) 2006-07-04 2008-01-02 삼성전자주식회사 일회 프로그래머블 소자, 이를 구비하는 전자시스템 및 그동작 방법
KR101468595B1 (ko) * 2008-12-19 2014-12-04 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
KR101669244B1 (ko) 2010-06-08 2016-10-25 삼성전자주식회사 에스램 소자 및 그 제조방법
KR101360947B1 (ko) * 2011-10-27 2014-02-10 윤재만 반도체 메모리 장치
JP2013161878A (ja) * 2012-02-02 2013-08-19 Renesas Electronics Corp 半導体装置、および半導体装置の製造方法
JP6128787B2 (ja) 2012-09-28 2017-05-17 キヤノン株式会社 半導体装置
US9112047B2 (en) * 2013-02-28 2015-08-18 Freescale Semiconductor, Inc. Split gate non-volatile memory (NVM) cell and method therefor
US9123546B2 (en) * 2013-11-14 2015-09-01 Taiwan Semiconductor Manufacturing Company Limited Multi-layer semiconductor device structures with different channel materials
CN104752393B (zh) * 2013-12-27 2017-11-03 中芯国际集成电路制造(上海)有限公司 Mos管电容器的布线结构及布线方法
US20150348874A1 (en) * 2014-05-29 2015-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Interconnect Devices and Methods of Forming Same
KR20170018813A (ko) 2014-06-16 2017-02-20 인텔 코포레이션 관통 실리콘 비아들(ｔｖｓ)의 사용 없이 로직 다이에의 메모리 다이의 직접 통합을 위한 방법
CN106463406A (zh) * 2014-06-16 2017-02-22 英特尔公司 硅管芯上的互连件叠置体中的嵌入式存储器
US9893278B1 (en) * 2016-08-08 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded memory device between noncontigous interconnect metal layers
JP2018026518A (ja) * 2016-08-12 2018-02-15 東芝メモリ株式会社 半導体記憶装置
KR102332456B1 (ko) * 2017-08-31 2021-12-02 마이크론 테크놀로지, 인크 두 개의 트랜지스터들과 하나의 캐패시터를 갖는 메모리 셀을 가지며, 기준 전압과 결합된 트랜지스터들의 바디 영역들을 갖는 장치
US10930595B2 (en) * 2017-09-28 2021-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Standard cells having via rail and deep via structures
KR102614728B1 (ko) * 2018-04-04 2023-12-19 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
US11374003B2 (en) * 2019-04-12 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit
US11049880B2 (en) * 2019-08-02 2021-06-29 Sandisk Technologies Llc Three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same
CN112635461B (zh) * 2020-12-08 2024-04-16 中国科学院微电子研究所 一种三维存算电路结构及其制备方法
CN113725301A (zh) * 2021-08-31 2021-11-30 上海积塔半导体有限公司 垂直型存储器件及其制备方法
CN114709168A (zh) * 2022-03-10 2022-07-05 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400715A (en) * 1980-11-19 1983-08-23 International Business Machines Corporation Thin film semiconductor device and method for manufacture
EP0251767A3 (en) 1986-06-30 1988-09-07 Canon Kabushiki Kaisha Insulated gate type semiconductor device and method of producing the same
JPH04192368A (ja) * 1990-11-23 1992-07-10 Sony Corp 縦チャンネルｆｅｔ
DE4433845A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
US6194290B1 (en) * 1998-03-09 2001-02-27 Intersil Corporation Methods for making semiconductor devices by low temperature direct bonding
EP1234332B1 (de) * 1999-11-15 2007-01-17 Infineon Technologies AG Dram-zellenstruktur mit tunnelbarriere
JP2001250913A (ja) * 1999-12-28 2001-09-14 Mitsumasa Koyanagi ３次元半導体集積回路装置及びその製造方法
JP3735855B2 (ja) * 2000-02-17 2006-01-18 日本電気株式会社 半導体集積回路装置およびその駆動方法

Also Published As

Publication number Publication date
CN1809914B (zh) 2010-06-09
JP2012253358A (ja) 2012-12-20
CN1809914A (zh) 2006-07-26
JP2012064950A (ja) 2012-03-29
KR20050003326A (ko) 2005-01-10
KR100904771B1 (ko) 2009-06-26

Similar Documents

Publication Publication Date Title
JP5294517B2 (ja) アッド‐オン層形成方法
JP5202842B2 (ja) 三次元集積回路構造及びこれを作る方法
JP7331119B2 (ja) 複数の機能性チップを伴う三次元ｎａｎｄメモリデバイスの集積
JP7242908B2 (ja) バックサイドアイソレーション構造体を備えた３次元メモリデバイス
JP2022535515A (ja) ３次元ｎａｎｄのためのキャパシタを形成するための構造および方法
US10896931B1 (en) 3D semiconductor device and structure
JP2022534538A (ja) ディープアイソレーション構造体を備えた３次元メモリデバイス
JP2022534615A (ja) ３次元ｎａｎｄのためのビットラインドライバーのアイソレーションのための構造および方法
US20190164834A1 (en) Methods to produce a 3d semiconductor memory device and system
US20200335399A1 (en) 3d semiconductor device and structure
US10388568B2 (en) 3D semiconductor device and system
US20180350685A1 (en) 3d semiconductor device and system
US20230335521A1 (en) Three-dimensional nand memory device and method of forming the same
US20190067110A1 (en) 3d semiconductor device and system
US20180350688A1 (en) 3d semiconductor device and system
US20180350689A1 (en) 3d semiconductor device and system
TW200931497A (en) Method of making a pillar pattern using triple or quadruple exposure
US20190109049A1 (en) 3d semiconductor device and system
US20190057903A1 (en) 3d semiconductor device and system
US20190074222A1 (en) 3d semiconductor device and system
US20190006240A1 (en) 3d semiconductor device and system
US20220336532A1 (en) Method to produce 3d semiconductor devices and structures with memory
US20180069052A1 (en) Semiconductor device and structure
WO2001017017A1 (fr) Memoire ferroelectrique remanente et son procede de fabrication
US11469271B2 (en) Method to produce 3D semiconductor devices and structures with memory

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120117

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121204

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130521

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130610

R150 Certificate of patent or registration of utility model

Ref document number: 5294517

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees