JP5285079B2 - はんだ合金および半導体装置 - Google Patents
はんだ合金および半導体装置 Download PDFInfo
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- JP5285079B2 JP5285079B2 JP2010534729A JP2010534729A JP5285079B2 JP 5285079 B2 JP5285079 B2 JP 5285079B2 JP 2010534729 A JP2010534729 A JP 2010534729A JP 2010534729 A JP2010534729 A JP 2010534729A JP 5285079 B2 JP5285079 B2 JP 5285079B2
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
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- C—CHEMISTRY; METALLURGY
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- C22C13/00—Alloys based on tin
- C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
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- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
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- C22C1/02—Making non-ferrous alloys by melting
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Description
最初に本実施の形態のはんだ合金およびそのはんだ合金を用いた半導体装置の構成について説明する。
たとえば厚さ0.25mmで7mm角のシリコンチップ2の表面にオーミック層5とメタライズ層6とが順に積層して形成される。また、たとえば厚さ1mmで10mm角の銅ブロックよりなる回路基板4の表面には、電解NiめっきによりNiめっき層9が形成される。
なお、上記において「Sn−10Sb−5Cu−0.1Ni−1In−0.05P(質量%)」とは、質量%でSbを10%、Cuを5%、Niを0.1%、Inを1%、Pを0.05%含み、かつ残部がSnと不可避的不純物よりなる組成を意味している。以下の記述において、これと同様の表記は同様の質量%における組成を意味するものとする。
SnにSbが添加された場合、引張強度が5質量%以上の添加で顕著に向上し、Sbの添加量増大に伴い向上し続ける。一方、伸びはSb添加量増大に伴い低下し20質量%で大きく低下する。はんだ材の引張強度が高くかつ伸びが低いと、はんだ層3で応力が緩和されずにシリコンチップ2が割れてしまう。よって半導体装置1の耐クラック性のためには、はんだ層3の引張強度と伸びが共に高いことが望ましい。これより半導体装置1の耐クラック性は、Sbの含有量が5質量%以上15質量%以下で優れている。
耐クラック性向上のために添加されたSbにより硬くなりすぎたはんだ材では応力緩和しないために半導体素子にチップ割れが生じてしまう。Inが添加されることにより、In相が分散されることによる延性強化で、割れにくく応力緩和する金属組織が形成される。一方、Inが添加されるとはんだ材の濡れ性が向上する。これは融点が低下されるために反応性が向上するためである。しかしながら、Inが活性な元素のため添加されすぎるとはんだ材が酸化されて濡れ性が低下する。またソルダーペーストであればポットライフが短くなる。すなわち長期保存性が低下する。さらに融点低下、耐熱性低下、高温軟化による耐クラック性低下が懸念される。したがって、適度なInの含有量が求められる。
(実施例1)
Sn−xSb(質量%:x=3、5、10、15、20、25、30、35、40)となるように純度99.5%のSnと、純度99.9%のSbとが合計で2kgになるように秤量された。その後、高周波溶解炉で最高温度が700℃になるまでSnが加熱された。その後Sbが投入され、攪拌され溶けきったことが確認された後、はんだ合金は速やかに直径40×長さ250mmの鋳型で鋳造された。はんだ合金は凝固後中央部を基準として直径25mm×長さ180mmの丸棒に機械加工され、引張試験のチャック部として直径25mm×長さ40mm、平行部直径8mm×長さ90mmにさらに機械加工された。そのはんだ合金に対し引張速度0.5mm/分の速度で引張試験が行われた。図5は、その引張試験での引張強度と伸びの測定結果を示している。図5は実施例1におけるSb含有量と引張強度および伸びとの関係を示した図である。
Sn−10Sb−1In−xCu−yNi(質量%:x=0、0.5、1.5、3、5、8、10,y=0、0.01、0.05、0.1、0.15、0.20)となるように各材料が秤量された。その後、各材料が窒素雰囲気中で高周波溶解され、700℃になったことと溶け残りがないことが確認された。その後幅20mm×高さ10mm×長さ150mmの鋳型で鋳塊が鋳造された。
次に、上述の製造方法で製造された半導体装置が各組成(比較例1〜30、実施例1〜12)につき各10個ずつ試作され、−50℃に30分、200℃に30分を1サイクルとした、500サイクルのヒートサイクル処理が行われた。表8は、これらについて、表面観察によるチップ割れ有無の結果を示している。またチップ対角線で断面研磨されたこれらについて、電子顕微鏡観察によるクラック率および残Ni厚の平均値の結果を示している。なお、チップ割れがあった場合はNGの印として×が記載され、割れていない場合はOKの印として○が記載されている。またチップが割れた場合は、クラック率は100%と記載されている。
表14は、Sn−12Sb−5Cu−0.08Niはんだ合金に、0、0.5、1、3、5、8、10質量%のInが添加されたはんだ合金ペレットが製造され、上述と同様の半導体装置が製造された際の、ボイド率について示している。また、コスト比は、Sn−12Sb−5Cu−0.08Niを1kg当たり3000円、インジウムを1kg当たり6万円とし、In添加合金価格/In無添加合金価格とした。図8は、実施例4におけるIn量とボイド率の平均との関係を示した図である。
上述の本実施の形態におけるはんだ層3に、P、Ge、Ga、Biよりなる群から選ばれる1種以上を合計で0.01質量%以上1質量%以下添加されたはんだ合金が製造された。そして、上術と同様の条件でそのはんだ合金を介して半導体素子であるシリコンチップ2に接続された金属電極である回路基板4を備えた半導体装置1が製造され、そのボイド率が測定された。その結果、全てのはんだ合金において、2%〜10%の改善効果がみられた。
本発明の実施の形態と同様の製造方法で、Sn−6Cuのはんだ合金ペレットを用いた半導体装置(比較例34)が作成された。このサンプルと実施例8の半導体装置1について、−50℃に30分、200℃に30分を500サイクルでヒートサイクル処理された。
上述の実施の形態と同様の実験が、回路基板にCu/Inver/Cu、Cu/Mo/Cuが用いられて行われた。Cu/Inver/Cuの各層の厚さは、0.4/0.4/0.4mmである。またCu/Mo/Cuの各層の厚さは、0.4/0.4/0.4mmである。
なお、半導体装置は、モジュール、パッケージ、基板に搭載されたもののいずれでも適用される。
Claims (4)
- Sbを5質量%以上15質量%以下、Cuを3質量%以上8質量%以下、Niを0.01質量%以上0.15質量%以下、Inを0.5質量%以上5質量%以下含み、残部がSnおよび不可避的不純物を含む、はんだ合金(3)。
- P、Ge、GaおよびBiよりなる群から選ばれる1種以上を合計で0.01質量%以上1質量%以下含有する、請求の範囲第1項に記載のはんだ合金(3)。
- 半導体素子(2)と、
請求の範囲第1項に記載のはんだ合金(3)を介して前記半導体素子(2)に接合された金属電極(4)とを備えた、半導体装置(1)。 - 前記半導体素子(2)と前記はんだ合金(3)との間および前記金属電極(4)と前記はんだ合金(3)との間の少なくともいずれかに、Cu−Ni−Snからなる化合物相(7a)と、Cu−Snからなる化合物相(7b)と、Sbを含有する含有相(7c)とを有する合金層(7)をさらに備えた、請求の範囲第3項に記載の半導体装置(1)。
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JPWO2010047139A1 (ja) | 2012-03-22 |
WO2010047139A1 (ja) | 2010-04-29 |
CN102196881B (zh) | 2014-06-04 |
CN102196881A (zh) | 2011-09-21 |
KR101285958B1 (ko) | 2013-07-12 |
US8598707B2 (en) | 2013-12-03 |
US20110198755A1 (en) | 2011-08-18 |
DE112009002570T5 (de) | 2012-06-21 |
KR20110059653A (ko) | 2011-06-02 |
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