CN102196881B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN102196881B
CN102196881B CN200980141900.5A CN200980141900A CN102196881B CN 102196881 B CN102196881 B CN 102196881B CN 200980141900 A CN200980141900 A CN 200980141900A CN 102196881 B CN102196881 B CN 102196881B
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quality
layer
addition
solder
alloy
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CN102196881A (zh
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前田晃
大津健嗣
山田朗
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
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    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
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    • B23K35/262—Sn as the principal constituent
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    • C22C1/02—Making non-ferrous alloys by melting
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Abstract

本发明的钎料合金(3)含有：5质量％以上15质量％以下的Sb、3质量％以上8质量％以下的Cu、0.01质量％以上0.15质量％以下的Ni、0.5质量％以上5质量％以下的In，其余部分包括Sn及不可避免的杂质。由此，可得到抑制半导体元件(2)的破裂，而且提高钎料材料的耐裂性的可靠性高的钎料合金(3)及半导体装置(1)。

Description

半导体装置
技术领域
本发明涉及钎料合金及半导体装置，特别是涉及适于半导体元件与电子线路的电极接合的、不含铅(无铅)的钎料合金及采用该钎料合金的半导体装置。 
背景技术
近年来，对半导体装置的可靠性的要求越来越高，特别是对热膨胀系数差大的半导体元件与电路基板的接合部要求高的耐热循环特性。现有的半导体元件多数使用硅(Si)或砷化镓(GaAs)作为基板，其工作温度为100℃～125℃。作为将其与电子线路的电极接合的钎料材料，从对起因于半导体元件与电路基板的热膨胀性差的反复热应力的耐裂性，用于与组装时的多步钎料接合相对应的高熔点，还有器件的耐污染性等考虑，Si器件中使用95Pb-5Sn(质量％)，砷化镓器件中使用80Au-20Sn(质量％)等。但是，从降低环境负荷的观点考虑，含有大量有害的铅(Pb)的95Pb-5Sn存在问题，另外从贵金属昂贵或储量的观点考虑，强烈希望80Au-20Sn作为替代材料。 
另一方面，从节能的观点考虑，作为下一代器件的以碳化硅(SiC)或氮化镓(GaN)作为基板的器件的开发正积极进行。从降低损耗的观点考虑，这些器件的工作温度应在175℃以上，也有人说将来达到300℃。 
针对上述要求，需要熔点高、且耐热性优良的高温钎料合金。这种高温钎料合金，例如，特开2004-298931号中已经公开。在该公报中，公开了一种含10～40质量％Sb、0.5～10质量％Cu、其余为Sn的高温无铅钎料合金及采用该钎料合金接合的电子部件。另外，公开了一种含有Ni、Co、Fe、Mo、Cr、Mn、Ag、Bi作为改善机械强度的元素的钎料合金，另外，公开了一种含有P、Ge、Ga作为抑制氧化元素的钎料合金。 
另外，例如，在特开2007-67158号公报中公开了即使在200℃的高温下仍得到充分的钎料接合强度的方法。在该公报的半导体装置中，从室温至200℃，采用含Cu-Sn化合物(例如，Cu6Sn5)相的Sn系钎料箔，对实施了Ni系镀敷的被连接材料加以连接，借此形成以Cu-Sn化合物作为主体的化合物层。该化合物层成为Ni系镀敷层与Sn系钎料的阻挡层，抑制了由连接界面反应引起的化合物成长。另外，在实施例中，Sn或Sn-3Ag(质量％)中含3质量％以上的Cu的钎料箔，与Ni系镀敷层接触，加热、熔融而加以接合。 
现有技术文献 
专利文献1：特开2004-298931号公报 
专利文献2：特开2007-67158号公报 
发明内容
发明所要解决的课题 
但是，专利文献1所示的钎料合金存在的问题是，钎料材料硬，故在钎料材料中不产生应力松弛，因此，由于热循环，半导体元件破裂。 
另外，专利文献2所示的半导体装置存在的问题是，由于钎料材料柔软，钎料材料易发生破裂，故钎料材料内部的耐裂性低。 
本发明是鉴于上述课题而提出的，其目的是提供一种通过控制钎料材料的硬度，抑制半导体元件的破裂，并且使钎料材料的耐裂性得到提高的可靠性高的钎料合金及半导体装置。 
解决课题的手段 
本发明的钎料合金，含有：5质量％以上15质量％以下的Sb、3质量％以上8质量％以下的Cu、0.01质量％以上0.15质量％以下的Ni、0.5质量％以上5质量％以下的In。其余部分包括Sn及不可避免的杂质。 
发明效果 
在本发明的钎料合金中，通过添加0.5质量％以上5质量％以下范围的In，在由于为了提高耐裂性添加的Sb而变得过硬的钎料材料内部分散柔软的In富裕相。由此，延展性得到强化，使钎料材料适度软化， 可以控制钎料材料的硬度。由此，抑制了半导体元件的破裂。另外，提高了钎料材料的耐裂性。 
附图说明
图1为本发明实施方案中采用钎料合金的半导体装置的概略断面图。 
图2为本发明实施方案中金属化层通过扩散而消失的硅基片与钎料层的接合部的放大的概略断面图。 
图3为显示本发明实施方案中半导体装置的钎料接合部产生的裂纹的发生状态的概略断面图。 
图4为显示本发明实施方案中半导体装置的硅基片中产生的裂纹的发生状态的概略断面图。 
图5为显示Sb含量与拉伸强度及延伸率的关系的图。 
图6为显示Cu量与残Ni厚度的平均值的关系的图。 
图7为显示Cu量与孔隙率的平均值的关系的图。 
图8为显示In量与孔隙率的平均值的关系的图。 
图9为以通过热循环处理后的断面观察而得到的硅基片的金属化层与钎料层的接合界面的电子显微镜及采用特性X射线的定性分析结果为基础模拟的概略断面图，图(A)对应于比较例34，图(B)对应于实施例8。 
图10为以通过热循环处理后的断面观察而得到的钎料层与Ni镀敷层的接合界面的电子显微镜及采用特性X射线的定性分析结果为基础模拟的概略断面图，图(A)对应于比较例34，图(B)对应于实施例8。 
具体实施方式
下面基于附图对本发明的实施方案加以说明。 
首先，对本实施方案的钎料合金及采用该钎料合金的半导体装置的构成加以说明。
图1为平视的沿半导体装置1的对角线的概略断面图。参照图1， 本实施方案的半导体装置1主要具有：作为半导体元件的例如硅基片2、作为钎料合金的钎料层3、作为金属电极的电路基板4、欧姆层5、金属化层6、合金层7和Ni(镍)镀敷层9。 
在该半导体装置1中，硅基片2通过钎料层3与电路基板4接合。在硅基片2与钎料层3之间形成有欧姆层5、金属化层6及合金层7。欧姆层5用于使硅基片2的半导体与金属的接合成为欧姆接合，以与硅基片2相接触的方式而形成。金属化层6用于获得欧姆层5与钎料层3的良好接合，以与欧姆层5相接触的方式而形成。合金层7是用钎料层3将硅基片2与电路基板4接合时，在钎料层3与金属化层6之间生成的层。 
作为欧姆层5，例如采用厚度100nm左右的Ti(钛)。另外，作为金属化层6，例如采用厚度500nm左右的Ni。作为合金层7，从硅基片2一侧例如形成Ni-Sn(锡)-Cu(铜)相，接着形成Cu-Sn相与Sn-Sb(锑)相的混合相。钎料层3，由含5质量％以上15质量％以下的Sb、3质量％以上8质量％以下的Cu、0.01质量％以上0.15质量％以下的Ni、0.5质量％以上5质量％以下的In，其余部分含Sn及不可避免的杂质的无铝钎料合金构成。 
在电路基板4与钎料层3之间，形成有Ni镀敷层9及合金层7。Ni镀敷层9是在电路基板4的表面采用电解镀Ni形成的层，例如，具有5μm左右的厚度。合金层7是用钎料层3将硅基片2与电路基板4接合时，在钎料层3与Ni镀敷层9之间生成的层。作为该合金层7，从电路基板4一侧，例如形成Ni-Sn-Cu相，接着形成Cu-Sn相与Sn-Sb相的混合相。 
下面，对该半导体装置1的制造方法加以说明。 
例如，在厚度0.25mm、7mm见方的硅基片2的表面，依次层叠欧姆层5与金属化层6而形成。另外，例如在厚度1mm、10mm见方的铜块构成的电路基板4的表面，采用电解镀Ni形成Ni镀敷层9。 
接着，采用钎料层3将硅基片2与电路基板4接合。在进行该钎料接合时，首先，在电路基板4的形成了Ni镀敷层9的表面上，设置形 成钎料层3的钎料小片。该钎料小片，例如由组成为Sn-10Sb-5Cu-0.1Ni-1In(铟)-0.05P(磷)(质量％)的合金构成，在其两面涂布焊剂。另外，该钎料小片例如具有厚度0.1mm、8mm见方的尺寸。 
在上述钎料小片上设置硅基片2。此时，以使钎料小片与金属化层6接触的方式设置硅基片2。 
在该状态下，将电路基板4与钎料小片与硅基片2加以堆叠，使电路基板4朝下放置于温度设定在280℃的加热板上，加热5分钟。由此，钎料小片发生熔融，形成熔融状态的钎料层3。另外，金属化层6中的成分与钎料层3中的成分互相扩散，在金属化层6与钎料层3之间形成合金层7。另外，Ni镀敷层9中的成分与钎料层3中的成分互相扩散，在Ni镀敷层9与钎料层3之间也形成合金层7。通过终止加热，熔融状态的钎料层3被冷却、固化。 
采用上述方法制造本实施方案的半导体装置1。 
还有，所谓上述“Sn-10Sb-5Cu-0.1Ni-1In-0.05P(质量％)”，意指按质量％计，含10％的Sb、5％的Cu、0.1％的Ni、1％的In、0.05％的P，并且其余部分为Sn和不可避免的杂质的组成。在以下的记载中，与其同样的表述意指同样的质量％的组成。 
下面，为了参照图2～图4，对耐裂性的评价指标加以说明，对在与图1同样构成的半导体装置1中硅基片2产生破裂的机理加以说明。 
欧姆层5与合金层7之间产生的剥离、合金层7与钎料层3之间产生的裂纹对硅基片2产生破裂的机理产生影响。 
第1，对欧姆层5与合金层7之间产生的剥离加以说明。图2为将半导体装置于200℃左右的高温下长时间保持直至金属化层消失后的硅基片2与钎料层3的接合部放大的概略断面图。参照图2，通过上述长时间高温保持，合金层7与欧姆层5之间的金属化层消失，合金层7与欧姆层5直接接触。另外，此时，欧姆层5的厚度与图1相比未发生变化，但合金层7由于金属化层和钎料层3的一部分通过热扩散渗入而成长变厚。当欧姆层5与合金层7形成直接接触的状态时，由于5、7两 者间的附着强度降低，结果采用较小的力就可以在欧姆层5与合金层7之间产生剥离8c。 
第2，对通过热循环处理，在合金层7与钎料层3之间产生的裂纹加以说明。图3表示以-50℃30分钟、200℃30分钟作为1次循环时，进行500次左右的热循环处理后，在钎料接合部产生的裂纹8a、8b的产生状态。参照图3，当对半导体装置1进行该热循环处理时，在硅基片2、钎料层3及电路基板4中热膨胀系数差最大的硅基片2与钎料层3之间从周围产生裂纹8a、8b。 
第3，对由于图2中说明的剥离8c及图3中说明的裂纹8a、8b造成的硅基片2产生破裂的机理加以说明。图4示出在热循环中途，金属化层6由于热扩散而消失时的半导体装置1的钎料接合部及硅基片2中产生的裂纹发生状况。参照图4，热循环开始后不久产生裂纹8a、8b。另外，当金属化层6消失时，在欧姆层5与合金层7的界面产生剥离8c。然后，通过裂纹8a、8b与剥离8c的复合，在硅基片2中产生破裂8d。 
下面，对半导体装置1的耐裂性加以说明。半导体装置1的耐裂性受作为钎料材料的钎料层3的耐裂性及作为半导体元件的硅基片2的破裂的影响。 
如图3所示，设裂纹8a、8b的投影长度分别为Ca、Cb。裂纹8a、8b，大概在硅基片2与钎料层3的界面，更详细地说，在合金层7与钎料层3的界面，大致直线地在钎料层3侧进行。因此，从合金层7与钎料层3的界面一端部向另一端部裂纹贯穿时的投影长度，与硅基片2与钎料层3的接合长度L几乎相等。因此，热循环的耐裂性，可用沿半导体装置1的对角线进行断面观察时的(Ca+Cb)/L×100(％)表示，将其作为开裂率(％)。 
还有，由于一般热扩散在钎料合金内不均匀发生，图4所示的剥离8c，有可能部分地在多个场所发生。此时，在裂纹8a与8b相连，贯穿合金层7与钎料层3的界面前，裂纹8a、8b及剥离8c相连，产生破裂8d。结果是硅基片2破裂而不能工作，所以，即使上述开裂率低，半导体装置1的耐裂性也变低。 
另外，当在钎料接合部内存在孔隙时，则产生以该部分作为基点的裂纹。另外，到达孔隙的裂纹进展很快。因此，当在钎料接合部内存在孔隙时，钎料层3的耐裂性及半导体装置1的耐裂性降低。 
因此，半导体装置1的耐裂性，可用热循环产生的硅基片2的破裂及产生破裂的循环数、通过断面观察的开裂率及半导体装置1制造后的钎料材料的孔隙率(钎料润湿性)表示。 
还有，所谓产生破裂的循环数，意指基片破裂可以确认时的热循环的循环数。而所谓孔隙率，如后面详细说明的，意指孔隙面积对钎料材料的断面积之比。当钎料的润湿性良好时，气泡的卷入变少，孔隙的发生被抑制，故孔隙率成为钎料润湿性的指标。 
下面，基于上述耐裂性的指标，对本实施方案的钎料合金的化学成分限定理由进行说明。 
第1，对Sb的含量(5质量％以上15质量％以下)加以说明。 
当在Sn中添加Sb时，在添加5质量％以上的情况下，拉伸强度显著提高，伴随着Sb添加量增大而连续提高。另一方面，延伸率伴随着Sb添加量增大而降低，在添加20质量％时显著降低。当钎料材料的拉伸强度高而延伸率低时，由于在钎料层3中应力得不到缓和，故硅基片2发生破裂。因此，为了半导体装置1的耐裂性，希望钎料层3的拉伸强度与延伸率均高。因此，半导体装置1的耐裂性在Sb含量为5质量％以上15质量％以下是优良的。 
另外，伴随着Sb添加量的增大，液相线温度上升，但固相线温度几乎不上升。在固液共存区域(固相线温度以上液相线温度以下的区域)，由于容易产生孔隙，故希望加热到液相线温度以上。Sb含量在15质量％时的液相线温度为300℃。由于一般的加热器的上限为300℃，只要Sb添加量在15质量％以下，就可以不采用特殊的加热装置进行加热，从这一点来说对成本是有利的。 
另外，因在固相线温度以上金属化层6的扩散速度显著加大，故希望固液共存区域(固相线温度以上液相线温度以下的区域)狭窄。Sb含量为15质量％时的固液共存区域的温度差为58℃，比20质量％时的 83℃狭窄。 
因此，通过添加5质量％以上15质量％以下的Sb，可以得到良好的耐裂性。另外，机械强度的平衡也良好。另外对成本也有利。 
第2，对Cu的含量(3质量％以上8质量％以下)及Ni含量(0.01质量％以上0.15质量％以下)加以说明。 
首先，对Cu的含量(3质量％以上8质量％以下)加以说明。伴随着Cu的添加量增大，延展性降低，孔隙率增大，残Ni厚度增大。延展性降低是由于通过Cu的添加，在占大部分的Sn的晶粒边界析出Cu6Sn5等金属间化合物，伴随着Cu的添加量增大，其析出量也增大，Sn的晶粒边界变得难以发生滑动所致。另外，孔隙率增大是由于伴随着Cu的添加量增大，液相线温度上升，析出的固相增多，因而粘度上升，焊剂的气体变得难以泄出所致。另外，残Ni厚度增大的原因是由于添加的Cu移动至熔融钎料中的接合界面，金属化层的Ni与作为主成分的Sn生成3元合金，其与Ni和Sn的2元合金相比，成长速度小所致。 
金属化层6的残Ni厚度的平均值，当Cu的添加量达到3质量％以上时显著增加。由此，抑制金属化层6的Ni扩散的效果得到发挥。但是，当Cu的添加量达到10质量％以上时，孔隙显著增加。从这些结果可知，通过向Sn-10Sb-1In基的合金中添加3质量％以上8质量％以下的Cu，可得到可靠性高的接合。 
还有，Cu的添加量，最希望Ni的扩散抑制效果、孔隙率、延展性的平衡均优良的5质量％左右。 
另外，在热循环处理中，如Ni添加量为0.01质量％以上0.15质量％以下、Cu的添加量在3质量％以上8质量％以下，则基片不发生破裂，开裂率在50％以下。 
下面，对Ni的含量(0.01质量％以上0.15质量％以下)加以说明。Ni添加量愈大，残Ni厚度平均值愈大。即，金属化层的扩散速度缓慢，高温下的接合强度得到长期保持。即，耐热性优良。该效果在0.01质量％以上显著。另一方面，Ni的添加量在0.2质量％以上孔隙显著增加。当孔隙多时，从半导体器件的散热方面考虑是不利的，因此现状是以约 0.15质量％以下作为标准。因此，通过把Ni添加量控制在0.15质量％以下，可得到可靠性高的接合。还有，关于Ni添加量的下限，即使小于0.01质量％也可以得到效果，但希望在效果显著呈现的0.01质量％以上。另外，关于Ni的添加量，最希望的是在焊接温度270℃下在接近Sn中的固溶界限的0.1质量％左右。 
第3，对In的含量(0.5质量％以上5质量％以下)加以说明。 
由于为了提高耐裂性所添加的Sb而变得过硬的钎料材料中不产生应力松弛，结果半导体元件中产生基片破裂。通过添加In，由In相分散而产生延展性强化，形成难以破裂的、应力松弛的金属组织。另一方面，当添加In时，钎料材料的润湿性提高。这是由于熔点降低，反应性提高所致。但是，由于In是活性元素，当过量添加时，使钎料材料氧化，润湿性降低。另外，如是焊膏，则贮存寿命变短。即，长期保存性降低。另外，还担心熔点降低、耐热性降低、高温软化引起的耐裂性降低。因此，要求适度的In含量。 
通过添加0.5质量％以上的In，可大幅降低孔隙率。另外，添加8质量％以上的In，孔隙率稍有上升。因此，In含量希望在0.5质量％以上5质量％以下。当考虑成本时，更希望在0.5质量％以上1质量％以下。 
还有，在本实施方案中，可用Ti(钛)作为欧姆层，但Ti以外的金属，可以采用例如Ni(镍)、Al(铝)、Mo(钼)、或含有Ti的这些元素的硅化物等化合物、或将这些组合的多层结构等。另外，也可以除去欧姆层。 
下面，对钎料合金加以说明，该钎料合金的特征在于，含有合计0.01质量％以上1质量％以下的选自P(磷)、Ge(锗)、Ga(镓)、Bi(铋)的1种以上。 
半导体装置1的孔隙率在全部钎料合金中具有2％～10％的改善效果。所述半导体装置1具备通过在上述实施方案中的钎料层3中，添加合计0.01质量％以上1质量％以下的选自P、Ge、Ga、Bi的1种以上的钎料合金而与作为半导体元件的硅基片2连接的作为金属电极的电路基板4。 
还有，合计含0.005质量％的选自P、Ge、Ga、Bi的1种以上的钎料合金，无显著的改善效果。另外，合计含1.5质量％及3质量％的选自P、Ge、Ga、Bi的1种以上的钎料合金，孔隙率反而上升。 
从这些结果可知，通过以合计0.01质量％以上1质量％以下的范围添加选自P、Ge、Ga、Bi的1种以上，可以抑制钎料合金的氧化，在使粘度降低的同时，也有使孔隙率降低的效果。 
下面，对用Cu/因瓦(Inver)/Cu、Cu/Mo/Cu作为电路基板的情况加以说明。在与上述实施方案同样的条件下，当用Cu/因瓦(Inver)/Cu、Cu/Mo/Cu作为电路基板时，Cu/因瓦(Inver)/Cu的开裂率为约1/2，而Cu/Mo/Cu为约1/3。另外，对电路基板4的表面未实施Ni镀敷的情况加以说明。在与上述实施方案同样的条件下，开裂率与金属化层的扩散均改善20％左右。 
如上所述，可以与电极材料和表面处理无关地获得效果。 
实施例 
下面对本发明的实施例加以详细说明。 
实施例1 
称取纯度99.5％的Sn与纯度99.9％的Sb合计2kg以成为Sn-xSb(质量％：x＝3、5、10、15、20、25、30、35、40)。然后，用高频熔化炉加热Sn，使最高温度达到700℃。然后加入Sb进行搅拌，确认熔化后，将钎料合金迅速用直径40×长度250mm的铸模进行铸造。以凝固后中央部作为基准，将钎料合金机械加工成直径25mm×长度180mm的圆棒，再机械加工成直径25mm×长度40mm、平行部直径8mm×长度90mm，作为拉伸试验的夹持部。对该钎料合金以拉伸速度0.5mm/分钟的速度进行拉伸试验。图5示出该拉伸试验中的拉伸强度与延伸率的测定结果。图5为显示实施例1中Sb含量与拉伸强度及延伸率的关系的图。 
还有，在上述拉伸试验片加工时，从2个夹持部附近用钻头采取切削粉末，用发光分析进行定量分析。其结果，确认以有效数字1位数含有如目标值的Sb。另外，通过外观检验，可以确认无钎料孔隙、表面缺陷及变色。 
由此可见，向Sn中添加Sb时，拉伸强度在添加5质量以上时显著提高，伴随着Sb的添加量增大显示连续提高的倾向，但对于延伸率，则伴随着Sb的添加量增大而降低，在20质量％时显著降低。 
另外，表1示出对延伸率显著降低的Sb为20质量％以下时(x＝0、5、10、15、20)的上述铸造样品，从大致的中央部取出几十毫克左右，用差示扫描热量分析装置(DSC)测定的固相线温度及液相线温度。在这里，以5℃/分钟的升温速度加热时得到的吸热曲线上最初出现的峰的最低温度定义为固相线温度。另外，以5℃/分钟冷却时得到的放热曲线上最初出现的峰的最高温度定义为液相线温度。 
[表1] 
  Sb(质量％)   0   5   10   15   20
  固相线温度   232℃   240℃   242℃   242℃   242℃
  液相线温度   232℃   242℃   265℃   300℃   325℃
实施例2 
称取各种材料以成为Sn-10Sb-1In-xCu-yNi(质量％：x＝0、0.5、1.5、3、5、8、10，y＝0、0.01、0.05、0.1、0.15、0.20)。然后，把各种材料在氮气气氛中进行高频熔化，确认达到700℃且无熔化残留物。然后，用宽20mm×高10mm×长度150mm的铸模铸造铸块。 
对该铸块的两端与中央部，用钻头采取切削粉末。对切削粉末的Sb、Cu、Ni，用等离子体熔融发光分析进行定量分析。其结果，确认以有效数字1位数得到如目标值的铸块。然后，把该铸块用轧机加工成厚度0.1mm。然后，将其表面用10％盐酸洗涤后加以充分水洗。然后，把该铸块用切割机切成8mm见方的小片状。此时，把轧制中产生部分破裂的用△表示，未破裂的用○表示，当为Sn-10Sb-1In(x＝y＝0)时，用◎(良好)表示，以内眼观察进行相对评价，作为延展性加以评价。采用此法，用上述制造方法各制造了10个半导体装置1。对这样制造的半导体装置1，采用透射X射线装置从硅基片表面入射X射线，将对得到的图像用图像处理装置加以双值化而得到的面积和的平均值作为平均孔隙率。另 外，用电子显微镜以2万倍对硅基片对角线断面研磨后的样品中央部进行观察，从照片上用5点平均算出残Ni厚度。表2示出对所制造的半导体装置1各10个进行平均的残Ni厚度的平均值和平均孔隙率的计算结果。图6及图7为这些计算结果的图。图6为显示实施例2中Cu量与残Ni厚度平均值的关系的图。图7为显示实施例2中Cu量与孔隙率平均值的关系的图。 
[表2] 
Figure BDA0000056725760000121
[表3] 
Figure BDA0000056725760000122
[表4] 
Figure BDA0000056725760000123
[表5] 
Figure BDA0000056725760000131
[表6] 
Figure BDA0000056725760000132
[表7] 
Figure BDA0000056725760000133
表2～7中的全部比较例1～30、实施例1～12均显示伴随着Cu的添加量增大，延展性降低、孔隙率增大、残Ni厚度增大的倾向。 
如图6所示，残Ni厚度的平均值，在Cu的添加量达到3质量％以上时显著增加，得到Ni金属化层的扩散抑制效果。但是，如图7所示，当Cu的添加量达到10质量％以上时，孔隙显著增加。由此表明，通过向Sn-10Sb-1In基的合金中添加3质量％以上8质量％以下的Cu，可得到可靠性高的接合。 
另外，如图6所示，Ni的添加量愈增大，残Ni厚度的平均值愈大。 这在Ni的添加量为0.01质量％以上时显著出现。另一方面，如图7所示，Ni的添加量在0.2质量％以上时，孔隙增加显著。当孔隙多时，在半导体元件的散热方面不利，目前的现状是以约0.15％以下作为标准。因此，关于Ni的添加量，通过控制在0.15质量％以下，显示可得到可靠性高的接合。关于Ni的添加量的下限，即使低于0.01质量％也可以得到效果，但希望在确认效果显现的0.01质量％以上。 
还有，在Sb添加量为5质量％及15质量％时的与上述同样的实验中，已确认也可以得到完全同样的效果。另外，关于硅基片，即使在采用几种不同大小和金属化规格的基片的与上述同样的实验中，也可以得到完全同样的效果。另外，即使在采用SiC(碳化硅)、GaN(氮化镓)基片的与上述同样的实验中，也可以得到完全同样的效果。 
实施例3 
接着，以各种组成(比较例1～30、实施例1～12)，试制各10个采用上述制造方法制造的半导体装置，以-50℃30分钟、200℃30分钟作为1次循环，进行500次循环的热循环处理。表8示出对这些样品通过表面观察而得到的基片有无破裂的结果。另外，示出对基片沿对角线进行断面研磨后的这些样品，用电子显微镜进行观察得到的开裂率及残Ni厚度平均值的结果。还有，当有基片破裂时，作为不良的符号用×表示，而无破裂时，作为良好的符号用○表示。另外，当基片破裂时，开裂率用100％表示。 
[表8] 
Figure BDA0000056725760000141
[表9] 
Figure BDA0000056725760000151
[表10] 
Figure BDA0000056725760000152
[表11] 
Figure BDA0000056725760000153
[表12] 
Figure BDA0000056725760000154
[表13] 
参照表8，比较例1～4的采用在Sn-10Sb-1In钎料合金中不添加Ni、以0～3质量％的范围添加Cu的钎料合金接合的半导体装置中，由于500次循环的热循环处理，作为金属化层的Ni未残存，因而发生基片破裂。另外，比较例5及比较例6的采用添加有5质量％或8质量％Cu的钎料合金接合的半导体装置，Ni金属化层部分地残存，但由于不残存部分的裂纹进展迅速，开裂率变得非常高。另外，比较例7的采用添加有10质量％Cu的钎料合金接合的半导体装置，由于钎料接合部有许多孔隙，裂纹进展迅速，虽然未产生基片破裂，但为贯穿状态。 
另外，参照表9，比较例8～10的采用添加有0.01质量％Ni、Cu添加量为1.5质量％以下的钎料合金接合的半导体装置，由于热循环使金属化层的Ni扩散，附着力降低，产生基片破裂。另外，比较例11的采用添加有10质量％Cu的钎料合金接合的半导体装置，由于孔隙多，裂纹进展迅速，裂纹为贯穿状态。在Cu的添加量为3质量％以上8质量％以下的实施例1～3中，基片不发生破裂，开裂率在50％以下。 
另外，比较例12、13、14、16、17、18、20、21、22的采用在Sn10Sb合金中添加0.05～0.15质量％Ni、添加1.5质量％以下Cu的钎料合金接合的半导体装置中，与Ni的添加量无关，Ni金属化层没有残存，发生基片破裂。另外，比较例15、19、23的采用在Sn10Sb1In合金中添加0.05～0.15质量％Ni、添加10质量％Cu的钎料合金接合的半导体装置，虽然Ni金属化层残存，但由于在钎料接合部中孔隙多，裂纹进展迅速，裂纹为贯穿状态。 
另外，比较例24～30的采用添加0.2质量％Ni的钎料合金接合的半导体装置，由于在钎料接合部中孔隙多，裂纹进展迅速，裂纹为贯穿状态。另外，在含1.5质量％以下Cu的比较例24～26中，发生基片破裂。 
从以上实施例可知，在Sn-10Sb-1In钎料合金中，通过添加0.01～0.15质量％Ni、3～8质量％范围Cu，可形成可靠性高的接合，可提供一种可靠性高的半导体装置。 
还有，已确认即使在采用Sb添加量在5质量％以上15质量％以下、且In添加量在0.5质量％以上5质量％以下的范围变化的钎料合金的与上述同样的实验中，也得到完全同样的效果。 
实施例4 
表14示出了在Sn-12Sb-5Cu-0.08Ni钎料合金中添加0、0.5、1、3、5、8、10质量％的In，制造钎料合金小片，进而制造与上述同样的半导体装置时的孔隙率。另外，设Sn-12Sb-5Cu-0.08Ni每公斤3000日元，铟每公斤6万日元，将成本比设为添加铟合金价格/不添加铟合金价格的比。图8为显示实施例4中In量与孔隙率平均值的关系的图。 
[表14] 
还有，已确认即使在采用Sb为5质量％以上15质量％以下、Cu为3质量％以上8质量％以下、Ni为0.01质量％以上0.15质量％以下、其余部分为Sn的钎料合金的与上述同样的实验中，也得到完全同样的效果。 
实施例5 
制造了在上述本实施方案的钎料层3中，添加合计0.01质量％以上1质量％以下的选自P、Ge、Ga、Bi的1种以上的钎料合金。而且，在与上述同样的条件下，制造了具备通过该钎料合金与作为半导体元件的硅基片2连接的作为金属电极的电路基板4的半导体装置1，测定了其孔隙率。其结果是，在全部钎料合金中具有2％～10％的改善效果。 
还有，合计含有0.005质量％的选自P、Ge、Ga、Bi的1种以上的钎料合金未能确认显著的改善效果。另外，合计含有1.5质量％及3质量％的选自P、Ge、Ga、Bi的1种以上的钎料合金，孔隙率反而显示上升的倾向。 
实施例6 
采用与本发明实施方案同样的制造方法，制成采用Sn-6Cu的钎料合金小片的半导体装置(比较例34)。对该样品与实施例8的半导体装置1以500次循环进行热循环处理，该循环为-50℃30分钟、200℃30分钟。 
在图9(A)示出的比较例34中，硅基片2与钎料层3之间的合金层7中存在Cu-Ni-Sn相7a及Cu-Sn相7b。另外，在图10(A)示出的比较例34中，电路基板4的表面形成的Ni镀敷层9与钎料层3之间的合金层7中存在Cu-Ni-Sn相7a及Cu-Sn相7b。由于硅基片2与电路基板4的热膨胀系数差所产生的热应力，沿比较柔软的钎料层3与Cu-Sn相7b的界面产生裂纹8e，并以较快的速度进展。 
另一方面，在图9(B)所示的实施例8中，作为半导体元件的硅基片2与作为钎料合金的钎料层3之间的合金层7中，除Cu-Ni-Sn相(含铜、镍和锡的相)7a及Cu-Sn相(含铜和锡的相)7b外，还存在含Sb相7c。另外，在图10(B)所示的实施例8中，在作为金属电极的电路基板4表面形成的Ni镀敷层9与作为钎料合金的钎料层3之间的合金层7中，除Cu-Ni-Sn相7a及Cu-Sn相7b外，还存在含Sb相7c。含Sb相7c，由于机械强度高，当裂纹8f碰上该相时，应力被分散，进展变得缓慢。另外，由于含Sb相7c在Cu-Ni-Sn相7a及Cu-Sn相7b 附近析出，Cu-Sn相7b的分散变得均匀，应力集中位置变少，故裂纹进展缓慢。因此使可靠性得到进一步的提高。 
还有，为了得到这种组织，在本次采用的半导体装置1中，必需以30℃/分钟以下的冷却速度加以接合。当采用比其高的速度急冷时，形成不均匀的组织，得不到显著的效果。 
实施例7 
电路基板采用Cu/因瓦(Inver)/Cu、Cu/Mo/Cu来进行与上述实施方案同样的实验。Cu/因瓦(Inver)/Cu的各层的厚度为0.4/0.4/0.4mm。Cu/Mo/Cu的各层的厚度为0.4/0.4/0.4mm。 
确认了Cu/因瓦(Inver)/Cu的开裂率为约1/2，Cu/Mo/Cu的开裂率为约1/3。另外，对还含有Cu、在电路基板表面不实施Ni镀敷时进行了同样的实验，但开裂率及金属化层的扩散均改善约20％左右。 
从上述可以确认，可以不依赖电极材料或表面处理得到效果。 
还有，半导体装置适用于任何安装在组件、插件、基板上的器件。 
应认为这里公开的实施方案及实施例在所有方面均为例示性的而非限制性的。本发明的范围不是由上述说明所示，而是通过权利要求范围加以表示，在与权利要求范围同等的含义及范围内的全部变更均包含在本发明中。 
产业上的利用可能性 
本发明特别适于不含铅的钎料合金及采用该钎料合金的半导体装置。 
符号的说明 
1半导体装置、2硅基片(半导体元件)、3钎料层(钎料合金)、4电路基板、5欧姆层、6金属化层、7合金层、7a Cu-Ni-Sn相、7b Cu-Sn相、7c含Sb相、8a、8b、8e、8f裂纹、8c剥离、8d破裂、9Ni镀敷层 

Claims (3)

1.一种半导体装置（1），其含有半导体元件（2）以及通过钎料合金（3）与上述半导体元件（2）接合的金属电极（4），所述钎料合金（3）含有：5质量%以上15质量%以下的Sb、3质量%以上8质量%以下的Cu、0.01质量%以上0.15质量%以下的Ni、0.5质量%以上5质量%以下的In、其余部分包括Sn及不可避免的杂质。
2.权利要求1所述的半导体装置（1），其合计含有0.01质量%以上1质量%以下的选自P、Ge、Ga以及Bi的1种以上。
3.权利要求1或2所述的半导体装置（1），其在上述半导体元件（2）与上述钎料合金（3）之间以及上述金属电极（4）与上述钎料合金（3）之间的至少任一者还具备合金层（7），所述合金层（7）具有包含Cu-Ni-Sn的化合物相（7a）、包含Cu-Sn的化合物相（7b）和包含Sb的含有相（7c）。
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