JP5281346B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5281346B2
JP5281346B2 JP2008238798A JP2008238798A JP5281346B2 JP 5281346 B2 JP5281346 B2 JP 5281346B2 JP 2008238798 A JP2008238798 A JP 2008238798A JP 2008238798 A JP2008238798 A JP 2008238798A JP 5281346 B2 JP5281346 B2 JP 5281346B2
Authority
JP
Japan
Prior art keywords
support plate
layer
wiring board
wiring
connection pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008238798A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010073838A5 (enExample
JP2010073838A (ja
Inventor
章夫 堀内
泰志 横田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008238798A priority Critical patent/JP5281346B2/ja
Priority to US12/542,987 priority patent/US20100065959A1/en
Publication of JP2010073838A publication Critical patent/JP2010073838A/ja
Publication of JP2010073838A5 publication Critical patent/JP2010073838A5/ja
Application granted granted Critical
Publication of JP5281346B2 publication Critical patent/JP5281346B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2008238798A 2008-09-18 2008-09-18 半導体装置及びその製造方法 Expired - Fee Related JP5281346B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008238798A JP5281346B2 (ja) 2008-09-18 2008-09-18 半導体装置及びその製造方法
US12/542,987 US20100065959A1 (en) 2008-09-18 2009-08-18 Semiconductor package and method of manufacturing the same, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008238798A JP5281346B2 (ja) 2008-09-18 2008-09-18 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2010073838A JP2010073838A (ja) 2010-04-02
JP2010073838A5 JP2010073838A5 (enExample) 2011-09-15
JP5281346B2 true JP5281346B2 (ja) 2013-09-04

Family

ID=42006468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008238798A Expired - Fee Related JP5281346B2 (ja) 2008-09-18 2008-09-18 半導体装置及びその製造方法

Country Status (2)

Country Link
US (1) US20100065959A1 (enExample)
JP (1) JP5281346B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11882652B2 (en) 2021-05-06 2024-01-23 Samsung Electro-Mechanics Co., Ltd. Printed circuit board

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5763887B2 (ja) * 2010-02-24 2015-08-12 千住金属工業株式会社 銅カラム及びその製造方法
JP2012164965A (ja) * 2011-01-21 2012-08-30 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
TWI739182B (zh) * 2019-10-24 2021-09-11 欣興電子股份有限公司 載板結構及其製作方法
CN113035789B (zh) * 2021-02-07 2022-07-05 深圳市星欣磊实业有限公司 一种to封装的高精度夹具及其使用方法
WO2023135720A1 (ja) * 2022-01-14 2023-07-20 キヤノン株式会社 モジュールおよび機器

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01217993A (ja) * 1988-02-26 1989-08-31 Hitachi Ltd 半導体装置
JP2658672B2 (ja) * 1991-10-11 1997-09-30 日本電気株式会社 Ｉ／ｏピンの修理構造および修理方法
US5288944A (en) * 1992-02-18 1994-02-22 International Business Machines, Inc. Pinned ceramic chip carrier
US5859470A (en) * 1992-11-12 1999-01-12 International Business Machines Corporation Interconnection of a carrier substrate and a semiconductor device
US5303862A (en) * 1992-12-31 1994-04-19 International Business Machines Corporation Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures
JPH07221104A (ja) * 1994-01-28 1995-08-18 Fujitsu Ltd 半導体装置の製造方法及び半導体装置及び電極ピン形成用マスク及び電極ピン形成用マスクを用いた試験方法
KR20070073984A (ko) * 1998-05-19 2007-07-10 이비덴 가부시키가이샤 프린트배선판 및 프린트배선판의 제조방법
JP2000058736A (ja) * 1998-08-07 2000-02-25 Sumitomo Kinzoku Electro Device:Kk 樹脂基板へのピン接続方法
JP3635219B2 (ja) * 1999-03-11 2005-04-06 新光電気工業株式会社 半導体装置用多層基板及びその製造方法
US6350664B1 (en) * 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JP3378550B2 (ja) * 2000-02-03 2003-02-17 日本特殊陶業株式会社 リードピン付き配線基板
US6660946B2 (en) * 2000-04-10 2003-12-09 Ngk Spark Plug Co., Ltd. Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin
US6555757B2 (en) * 2000-04-10 2003-04-29 Ngk Spark Plug Co., Ltd. Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions
JP2004228595A (ja) * 2000-04-10 2004-08-12 Ngk Spark Plug Co Ltd ピン立設樹脂製基板、ピン立設樹脂製基板の製造方法、ピン及びピンの製造方法
TW503546B (en) * 2000-10-13 2002-09-21 Ngk Spark Plug Co Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin
TW557559B (en) * 2001-07-27 2003-10-11 Ngk Spark Plug Co Resin-made substrate on which there is installed with a vertically installed pin, manufacturing method thereof, and manufacturing method for pin
US6974765B2 (en) * 2001-09-27 2005-12-13 Intel Corporation Encapsulation of pin solder for maintaining accuracy in pin position
JP3615727B2 (ja) * 2001-10-31 2005-02-02 新光電気工業株式会社 半導体装置用パッケージ
JP4541763B2 (ja) * 2004-01-19 2010-09-08 新光電気工業株式会社 回路基板の製造方法
TWI255022B (en) * 2004-05-31 2006-05-11 Via Tech Inc Circuit carrier and manufacturing process thereof
JP2008277525A (ja) * 2007-04-27 2008-11-13 Shinko Electric Ind Co Ltd ピン付き基板並びに配線基板および半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11882652B2 (en) 2021-05-06 2024-01-23 Samsung Electro-Mechanics Co., Ltd. Printed circuit board

Also Published As

Publication number Publication date
US20100065959A1 (en) 2010-03-18
JP2010073838A (ja) 2010-04-02

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