JP5269799B2 - ウエハのバイア形成 - Google Patents

ウエハのバイア形成 Download PDF

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Publication number
JP5269799B2
JP5269799B2 JP2009533462A JP2009533462A JP5269799B2 JP 5269799 B2 JP5269799 B2 JP 5269799B2 JP 2009533462 A JP2009533462 A JP 2009533462A JP 2009533462 A JP2009533462 A JP 2009533462A JP 5269799 B2 JP5269799 B2 JP 5269799B2
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JP
Japan
Prior art keywords
groove
wafer
forming
completed wafer
back surface
Prior art date
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Expired - Fee Related
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JP2009533462A
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English (en)
Japanese (ja)
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JP2010507260A5 (https=
JP2010507260A (ja
Inventor
ジョン・トレッツァ
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Cufer Asset Ltd LLC
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Cufer Asset Ltd LLC
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Publication of JP2010507260A5 publication Critical patent/JP2010507260A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
JP2009533462A 2006-10-17 2007-10-15 ウエハのバイア形成 Expired - Fee Related JP5269799B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US82977206P 2006-10-17 2006-10-17
US60/829,772 2006-10-17
PCT/US2007/081380 WO2008048925A2 (en) 2006-10-17 2007-10-15 Wafer via formation

Publications (3)

Publication Number Publication Date
JP2010507260A JP2010507260A (ja) 2010-03-04
JP2010507260A5 JP2010507260A5 (https=) 2013-02-07
JP5269799B2 true JP5269799B2 (ja) 2013-08-21

Family

ID=39314773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009533462A Expired - Fee Related JP5269799B2 (ja) 2006-10-17 2007-10-15 ウエハのバイア形成

Country Status (6)

Country Link
US (1) US7871927B2 (https=)
EP (1) EP2074647B1 (https=)
JP (1) JP5269799B2 (https=)
KR (1) KR101175393B1 (https=)
CN (1) CN101553903B (https=)
WO (1) WO2008048925A2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916754B (zh) * 2010-06-29 2012-08-29 香港应用科技研究院有限公司 通孔和通孔形成方法以及通孔填充方法
WO2012119333A1 (zh) * 2011-03-04 2012-09-13 中国科学院微电子研究所 穿硅通孔结构及其形成方法
US8486805B2 (en) 2011-03-04 2013-07-16 Institute of Microelectronics, Chinese Academy of Sciences Through-silicon via and method for forming the same
CN102683308B (zh) * 2011-03-11 2015-02-04 中国科学院微电子研究所 穿硅通孔结构及其形成方法
US20130015504A1 (en) * 2011-07-11 2013-01-17 Chien-Li Kuo Tsv structure and method for forming the same
JP5834563B2 (ja) * 2011-07-14 2015-12-24 セイコーエプソン株式会社 半導体装置の製造方法
MY201172A (en) * 2018-09-19 2024-02-08 Intel Corp Stacked through-silicon vias for multi-device packages

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Also Published As

Publication number Publication date
US7871927B2 (en) 2011-01-18
CN101553903A (zh) 2009-10-07
KR20090076914A (ko) 2009-07-13
EP2074647A4 (en) 2010-07-28
WO2008048925A3 (en) 2008-07-03
EP2074647B1 (en) 2012-10-10
JP2010507260A (ja) 2010-03-04
KR101175393B1 (ko) 2012-08-20
US20080090413A1 (en) 2008-04-17
WO2008048925A2 (en) 2008-04-24
EP2074647A2 (en) 2009-07-01
CN101553903B (zh) 2012-08-29

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