Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
  • H10W20/2125—Top-view shapes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes

Definitions

• the thickness of only select portions of the wafer will be reduced.
• the thickness is such that the above- referenced via approaches can be used and an appropriate seed layer can be deposited.
• the overall structural rigidity of the wafer can be retained to the extent necessary to allow for the necessary handling.
• regions where the thickness is to be reduced can be limited to areas where vias are to be located and can be etched in large fashion using coarse etching techniques if desired because the boundaries are not critical. In fact, in some cases, post via-formation thinning will remove the boundaries entirely.
• One implementation of the approach for electrically conductive via formation in a fully processed wafer involves defining at least one trench area on a backside of the fully processed wafer, forming at least one trench within the trench area to an overall depth that will allow for a via formed within the trench to be seeded over its full length, forming the via within the trench into the fully processed wafer to a predetermined depth, depositing a seed layer over the full length of the via, and plating the seed layer to fill the via with an electrically conductive metal.
• FIGS. IA through IH illustrate, in simplified form, one example approach of the "trench" technique
• FIG. 2 illustrates, in simplified form, a wafer using one example approach as described herein;
• FIGS. 3 A through 3L illustrate a variant of the aforementioned approach involving two or more "stacked" trenches.
• FIG. 4 is a photograph of a portion of a wafer created using one of the approaches described herein.
• Our approach is a "trench" technique that involves first etching regions of the backside of the fully formed wafer to allow the wafer to be thin in those regions where it needs to be for deep via formation while allowing proper seed deposition, while a large portion of the wafer is maintained either at full thickness or some pre-thinned thickness that still maintains the wafer at a thickness and overall rigidity that will allow it to be further handled in a routine manner.
• the thinned regions can: i) cover an area equal to or exceeding the area of an individual chip as it will exist once diced; ii) cover smaller areas where groups of vias will be formed; or iii) cover only those individual areas where individual vias will be formed. [0016] For purposes of consistency, such a reduced area will be referred to herein as a
• these trenches can be created so that they can assist in some later- performed step as will be described in greater detail below.
• the total area of the trenches relative as a fraction of the overall area of the wafer should typically be under 75% and typically 50% or less to ensure the structural integrity of the wafer and ability for it to be handled in a conventional manner is maintained.
• trench formation can be done with the same etch processes used for forming the vias.
• the trench(es) can be formed using a lower- precision process like a wet-etch process.
• the trench depth can be greater or lesser depending upon the via diameter and depth.
• the trench depth needed is one that will allow for a via that is formed into the wafer within the trench to be seeded to its complete depth.
• a wafer with an overall thickness of 750um would only require a trench that would render the wafer 400um thick in the required area if 50um diameter vias were to be created, or a trench to render the wafer 150um thick if lOum diameter vias were to be made.
• deeper trenches i.e. thinner wafer regions
• a multi- stepped approach can be used in which two or more "stacked trenches" are used to bring the wafer down to the necessary reduced thickness while maintaining the overall structural integrity.
• FIGS. IA through IG illustrate, in simplified form, one example approach of the "trench" technique.
• FIG IA illustrates, in simplified form, a part of a semiconductor wafer 100.
• the semiconductor is full thickness and ready for dicing, in that both front end and backend processing are complete.
• the wafer will also be processed to add vias from the back side down to some portion of one of the layers of metalization placed as part of the backend processing.
• a trench 102 is formed over the area where the deep metal filled vias will be, but the wafer is too thick to allow for either via etching down to the depth required, seed deposition or both.
• the trench area 104 is defined and formed using, for example, a conventional dry etch or wet etch approach down to a depth 106 sufficient to define a new outer surface 108, of sufficient distance from (in this example) the metalization point 110 that will be connected to, and to meet the criteria necessary for via creation and seed deposition down to that metalization point 110.
• the surface shape of the trench 102 is limited only by the ability to define it. Thus, depending upon the particular application, any shape from a simple quadrilateral or circular shape to a highly complex geometric shape can be used.
• the via is formed in the desired manner. As shown in FIGS. 1C through
• FIG. IG for purposes of illustration, an annular via approach such as described in the above- referenced patent applications is used.
• the via 110 on the left will extend to an intermediate point 110 in the metalization layers, whereas the via 112 on the right will only extend to the first metalization layer 116.
• the vias 110, 112 are of different depths, they would not be formed at the same time, but rather, vias of a common depth would be created at the same time if they had the same diameter.
• the annular vias 110, 112 are not in any way shown to scale and, in fact all proportions are grossly exaggerated and out of scale.
• an annular ring shaped via trench 118 is formed. As shown in FIG. ID, the via trench 118 is filled with an insulator 120. As shown in FIG. IE, the inner island of semiconductor material 122 within the insulator 120 is removed. As shown in FIG. IF, a seed layer 124 is deposited and the via filled with metal 126 using, in this example, an electroplating process. Thereafter, any additional desired processing steps, such as formation of device pads or other acts not relevant to understanding the process, are performed.
• the wafer will either simply be sawn or diced (for the former case) or it can now be thinned to provide access to the contacts 128, 130 formed by the metal-filled vias and then diced or sawn.
• the newly formed vias can be used as posts 132, 134, in other implementation variants, the vias can have contact pads 128, 130 attached to them.
• the approach was illustrated for a pair of vias, the approach would be the same for a single via or for multiple vias (from two to literally hundreds or more), the only difference being the size or shape of the trench that would be used.
• FIG. 2 illustrates, in simplified form, a wafer 200 using one example approach as described herein, both from the trench side (FIG. 2A) and, in cross section taken at A — A (FIG. 2B).
• the trenches 202 are sized and shaped so as to be aligned with, and slightly larger than, the individual chips 204 formed on the wafer 200.
• FIGS. 3 A through 3L illustrate a variant of the aforementioned approach involving two or more "stacked" trenches to accommodate, for example, extremely narrow vias in a thick wafer or specific contact formation requirements.
• FIG. 3 A 300, a simplified portion of which is shown in FIG. 3 A.
• a trench 302 is formed in the back side 304 of the wafer
• a pair of smaller trenches 308, 310 are formed in the bottom surface 312 of the first trench 302 in the same way as the first trench 302 was formed.
• the "same way” merely means that the lower surface 312 of the first trench 302is treated as a starting surface (i.e. like the original surface 314 of the wafer 300 before the first trench 302 was formed). It is not intended to imply that the identical approach used to form the first trench must be used - the same or a different approach could be used.
• the distance between the bottom surface 316 of the secondary trenches 308, 310 and the desired connection points 318, 320 will be within the necessary range to allow for seed deposit with the intended via sizing.
• annular via 322, 324 is created that extends from the bottom 316 of the secondary trench 308, 310 to the respective desired connection points 318, 320, here again, a respective point in the metalization layers.
• the thickness of a significant portion of the wafer remains at the original surface 314 to connection point 318 thickness N.
• an even greater portion of the wafer 300 remains at a thickness of N - Z and only a small portion of the wafer is at a thickness of N - (Y + Z).
• this multi-depth (or multiple stepped) approach a flexibility in selecting the depths Y and Z is available without significant risk of weakening the wafer.
• FIG. 3E illustrates a view of the portion of the wafer 300 taken from the trench side.
• FIG. 3E therefore, provides an alternate view of surfaces "a", “b", and “c” and the annular trench "d".
• FIG. 3F shows the wafer 300 after the annular vias 322, 324 have been filled with an insulator 326.
• FIG. 3G shows the wafer 300 after the island 328 of semiconductor material within the annular insulator 326 has been removed down to the desired metalization connection point 318, 320.
• FIG. 3H shows the wafer 300 after the void has been seeded 322 and filled with metal 324.
• the wafer 300 can be diced and the chips, can be thinned to expose the newly formed contacts 326, 328, or the wafer 300 can be thinned before dicing - in either case followed by, for example, creation of contact pads 330, 332 if desired or necessary (FIG. 3J).
• the wafer or chip if diced was related to the point to be connected to as opposed to the overall via pitch and the secondary trenches were appropriately sized and spaced
• the wafer or chip if diced
• the secondary vias could themselves be filled with a conductor 334, such as shown in FIG. 3L, before, or as part of, a contact pad formation process. In this manner, greater wafer or chip thickness can be maintained.
• FIG. 4 is a photograph of a portion of a wafer created using one of the above approaches. As can be seen, in the approach of FIG. 4, multiple trenches are used within the boundaries of a single chip, in this case on an individual via basis.
• the trenches can be formed so as to serve other purposes as well.
• the trenches can be designed to help channel insulator into an annular trench or to confine metal that will become or otherwise form a rerouting trace.
• the trenches can advantageously serve multiple purposes beyond merely addressing the via depth problem noted above.

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• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Electroplating Methods And Accessories (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

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• 2007
  • 2007-10-15 JP JP2009533462A patent/JP5269799B2/ja not_active Expired - Fee Related
  • 2007-10-15 CN CN2007800375496A patent/CN101553903B/zh not_active Expired - Fee Related
  • 2007-10-15 WO PCT/US2007/081380 patent/WO2008048925A2/en not_active Ceased
  • 2007-10-15 US US11/872,083 patent/US7871927B2/en not_active Expired - Fee Related
  • 2007-10-15 KR KR1020097007578A patent/KR101175393B1/ko not_active Expired - Fee Related
  • 2007-10-15 EP EP07844296A patent/EP2074647B1/en not_active Not-in-force

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