JP5237607B2 - 基板の製造方法 - Google Patents

基板の製造方法 Download PDF

Info

Publication number
JP5237607B2
JP5237607B2 JP2007277438A JP2007277438A JP5237607B2 JP 5237607 B2 JP5237607 B2 JP 5237607B2 JP 2007277438 A JP2007277438 A JP 2007277438A JP 2007277438 A JP2007277438 A JP 2007277438A JP 5237607 B2 JP5237607 B2 JP 5237607B2
Authority
JP
Japan
Prior art keywords
substrate
pad
semiconductor substrate
electrode
forming step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007277438A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009105311A (ja
JP2009105311A5 (https=
Inventor
秀明 坂口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007277438A priority Critical patent/JP5237607B2/ja
Priority to US12/257,697 priority patent/US7867894B2/en
Priority to TW097140818A priority patent/TW200926381A/zh
Priority to EP08167664A priority patent/EP2053651B1/en
Publication of JP2009105311A publication Critical patent/JP2009105311A/ja
Publication of JP2009105311A5 publication Critical patent/JP2009105311A5/ja
Application granted granted Critical
Publication of JP5237607B2 publication Critical patent/JP5237607B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/804—Containers or encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07131—Means for applying material, e.g. for deposition or forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)
JP2007277438A 2007-10-25 2007-10-25 基板の製造方法 Active JP5237607B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007277438A JP5237607B2 (ja) 2007-10-25 2007-10-25 基板の製造方法
US12/257,697 US7867894B2 (en) 2007-10-25 2008-10-24 Method for producing substrate
TW097140818A TW200926381A (en) 2007-10-25 2008-10-24 Method for producing substrate
EP08167664A EP2053651B1 (en) 2007-10-25 2008-10-27 Method for producing substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007277438A JP5237607B2 (ja) 2007-10-25 2007-10-25 基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009105311A JP2009105311A (ja) 2009-05-14
JP2009105311A5 JP2009105311A5 (https=) 2010-09-09
JP5237607B2 true JP5237607B2 (ja) 2013-07-17

Family

ID=40262148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007277438A Active JP5237607B2 (ja) 2007-10-25 2007-10-25 基板の製造方法

Country Status (4)

Country Link
US (1) US7867894B2 (https=)
EP (1) EP2053651B1 (https=)
JP (1) JP5237607B2 (https=)
TW (1) TW200926381A (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GR20080100491A (el) * 2008-07-23 2010-02-24 Διονυσιος Χαραλαμπους Χοϊδας Συσκευη κινητης τηλεφωνιας με ενσωματωμενη διαταξη επαληθευσης των ενδειξεων του ταξιμετρου ενος μισθωμενου οχηματος
JP5578808B2 (ja) * 2009-05-15 2014-08-27 新光電気工業株式会社 半導体パッケージ
JP5644242B2 (ja) 2009-09-09 2014-12-24 大日本印刷株式会社 貫通電極基板及びその製造方法
JP2011187771A (ja) * 2010-03-10 2011-09-22 Omron Corp 電極部の構造
EP2482310B1 (en) * 2011-01-27 2020-09-23 Sensirion AG Through vias in a sensor chip
JP5821284B2 (ja) * 2011-05-30 2015-11-24 セイコーエプソン株式会社 配線基板、赤外線センサー及び貫通電極形成方法
JP6031746B2 (ja) * 2011-11-01 2016-11-24 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置及び電子機器
US9653401B2 (en) * 2012-04-11 2017-05-16 Nanya Technology Corporation Method for forming buried conductive line and structure of buried conductive line
EP2871152B1 (en) 2013-11-06 2017-05-24 Sensirion AG Sensor device
EP3001186B1 (en) 2014-09-26 2018-06-06 Sensirion AG Sensor chip
EP3032227B1 (en) 2014-12-08 2020-10-21 Sensirion AG Flow sensor package

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3648585B2 (ja) * 1997-05-27 2005-05-18 カシオ計算機株式会社 半導体装置及びその製造方法
US6943056B2 (en) * 2002-04-16 2005-09-13 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
JP2004095849A (ja) 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
US6790775B2 (en) * 2002-10-31 2004-09-14 Hewlett-Packard Development Company, L.P. Method of forming a through-substrate interconnect
JP2005026582A (ja) * 2003-07-04 2005-01-27 Olympus Corp 半導体装置及びその半導体装置の製造方法
JP4524156B2 (ja) * 2004-08-30 2010-08-11 新光電気工業株式会社 半導体装置及びその製造方法
JP4528100B2 (ja) * 2004-11-25 2010-08-18 新光電気工業株式会社 半導体装置及びその製造方法
US7307348B2 (en) * 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
KR100753528B1 (ko) * 2006-01-04 2007-08-30 삼성전자주식회사 웨이퍼 레벨 패키지 및 이의 제조 방법
US7659612B2 (en) * 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US8034702B2 (en) * 2007-08-16 2011-10-11 Micron Technology, Inc. Methods of forming through substrate interconnects

Also Published As

Publication number Publication date
JP2009105311A (ja) 2009-05-14
EP2053651A2 (en) 2009-04-29
EP2053651B1 (en) 2013-03-06
TW200926381A (en) 2009-06-16
US20090117738A1 (en) 2009-05-07
EP2053651A3 (en) 2011-11-16
US7867894B2 (en) 2011-01-11

Similar Documents

Publication Publication Date Title
JP5237607B2 (ja) 基板の製造方法
JP5808586B2 (ja) インターポーザの製造方法
JP4361826B2 (ja) 半導体装置
JP5280945B2 (ja) 半導体装置及びその製造方法
JP5608605B2 (ja) 配線基板の製造方法
JP5535494B2 (ja) 半導体装置
JP5563785B2 (ja) 半導体パッケージ及びその製造方法
JP5275400B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP2006049424A (ja) 電子部品内蔵基板およびその製造方法
JP2008300782A (ja) 貫通電極付き基板の製造方法
JP6606331B2 (ja) 電子装置
JP2012033973A (ja) 配線基板及び半導体パッケージ
JP2010103398A (ja) 電子部品内蔵基板及びその製造方法
JP5357239B2 (ja) 配線基板、半導体装置、及び配線基板の製造方法
JP2010103133A (ja) 配線基板及びその製造方法
JP2015198094A (ja) インターポーザ、半導体装置、およびそれらの製造方法
JP2010245509A (ja) 半導体装置
JP2011129844A (ja) 電子装置およびその製造方法
JP5479638B2 (ja) 配線基板
JP2011187912A (ja) 電子素子内蔵型印刷回路基板及びその製造方法
JP6533066B2 (ja) 電子装置
JP4528018B2 (ja) 半導体装置及びその製造方法
JP4955259B2 (ja) 配線基板、半導体装置、及び配線基板の製造方法
JP2007194472A (ja) 薄膜キャパシタの製造方法
JP2011238742A (ja) 配線基板の製造方法及び配線基板

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100726

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100726

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121218

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121219

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130212

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130312

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130329

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5237607

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160405

Year of fee payment: 3