JP5237607B2 - 基板の製造方法 - Google Patents
基板の製造方法 Download PDFInfo
- Publication number
- JP5237607B2 JP5237607B2 JP2007277438A JP2007277438A JP5237607B2 JP 5237607 B2 JP5237607 B2 JP 5237607B2 JP 2007277438 A JP2007277438 A JP 2007277438A JP 2007277438 A JP2007277438 A JP 2007277438A JP 5237607 B2 JP5237607 B2 JP 5237607B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007277438A JP5237607B2 (ja) | 2007-10-25 | 2007-10-25 | 基板の製造方法 |
| US12/257,697 US7867894B2 (en) | 2007-10-25 | 2008-10-24 | Method for producing substrate |
| TW097140818A TW200926381A (en) | 2007-10-25 | 2008-10-24 | Method for producing substrate |
| EP08167664A EP2053651B1 (en) | 2007-10-25 | 2008-10-27 | Method for producing substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007277438A JP5237607B2 (ja) | 2007-10-25 | 2007-10-25 | 基板の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009105311A JP2009105311A (ja) | 2009-05-14 |
| JP2009105311A5 JP2009105311A5 (enExample) | 2010-09-09 |
| JP5237607B2 true JP5237607B2 (ja) | 2013-07-17 |
Family
ID=40262148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007277438A Active JP5237607B2 (ja) | 2007-10-25 | 2007-10-25 | 基板の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7867894B2 (enExample) |
| EP (1) | EP2053651B1 (enExample) |
| JP (1) | JP5237607B2 (enExample) |
| TW (1) | TW200926381A (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GR20080100491A (el) * | 2008-07-23 | 2010-02-24 | Διονυσιος Χαραλαμπους Χοϊδας | Συσκευη κινητης τηλεφωνιας με ενσωματωμενη διαταξη επαληθευσης των ενδειξεων του ταξιμετρου ενος μισθωμενου οχηματος |
| JP5578808B2 (ja) * | 2009-05-15 | 2014-08-27 | 新光電気工業株式会社 | 半導体パッケージ |
| JP5644242B2 (ja) | 2009-09-09 | 2014-12-24 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法 |
| JP2011187771A (ja) * | 2010-03-10 | 2011-09-22 | Omron Corp | 電極部の構造 |
| EP2482310B1 (en) * | 2011-01-27 | 2020-09-23 | Sensirion AG | Through vias in a sensor chip |
| JP5821284B2 (ja) * | 2011-05-30 | 2015-11-24 | セイコーエプソン株式会社 | 配線基板、赤外線センサー及び貫通電極形成方法 |
| JP6031746B2 (ja) * | 2011-11-01 | 2016-11-24 | セイコーエプソン株式会社 | 半導体装置の製造方法、半導体装置及び電子機器 |
| US9653401B2 (en) * | 2012-04-11 | 2017-05-16 | Nanya Technology Corporation | Method for forming buried conductive line and structure of buried conductive line |
| EP2871152B1 (en) | 2013-11-06 | 2017-05-24 | Sensirion AG | Sensor device |
| EP3001186B1 (en) | 2014-09-26 | 2018-06-06 | Sensirion AG | Sensor chip |
| EP3032227B1 (en) | 2014-12-08 | 2020-10-21 | Sensirion AG | Flow sensor package |
| JP2016029731A (ja) * | 2015-10-02 | 2016-03-03 | セイコーエプソン株式会社 | 回路基板及びセンサー |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3648585B2 (ja) * | 1997-05-27 | 2005-05-18 | カシオ計算機株式会社 | 半導体装置及びその製造方法 |
| US6943056B2 (en) * | 2002-04-16 | 2005-09-13 | Renesas Technology Corp. | Semiconductor device manufacturing method and electronic equipment using same |
| JP2004095849A (ja) * | 2002-08-30 | 2004-03-25 | Fujikura Ltd | 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法 |
| US6790775B2 (en) * | 2002-10-31 | 2004-09-14 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
| JP2005026582A (ja) * | 2003-07-04 | 2005-01-27 | Olympus Corp | 半導体装置及びその半導体装置の製造方法 |
| JP4524156B2 (ja) * | 2004-08-30 | 2010-08-11 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
| JP4528100B2 (ja) * | 2004-11-25 | 2010-08-18 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
| US7307348B2 (en) * | 2005-12-07 | 2007-12-11 | Micron Technology, Inc. | Semiconductor components having through wire interconnects (TWI) |
| KR100753528B1 (ko) * | 2006-01-04 | 2007-08-30 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 및 이의 제조 방법 |
| US7659612B2 (en) * | 2006-04-24 | 2010-02-09 | Micron Technology, Inc. | Semiconductor components having encapsulated through wire interconnects (TWI) |
| US8034702B2 (en) * | 2007-08-16 | 2011-10-11 | Micron Technology, Inc. | Methods of forming through substrate interconnects |
-
2007
- 2007-10-25 JP JP2007277438A patent/JP5237607B2/ja active Active
-
2008
- 2008-10-24 US US12/257,697 patent/US7867894B2/en not_active Expired - Fee Related
- 2008-10-24 TW TW097140818A patent/TW200926381A/zh unknown
- 2008-10-27 EP EP08167664A patent/EP2053651B1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP2053651A3 (en) | 2011-11-16 |
| JP2009105311A (ja) | 2009-05-14 |
| EP2053651B1 (en) | 2013-03-06 |
| TW200926381A (en) | 2009-06-16 |
| US7867894B2 (en) | 2011-01-11 |
| US20090117738A1 (en) | 2009-05-07 |
| EP2053651A2 (en) | 2009-04-29 |
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