JP5231931B2 - Pll回路 - Google Patents
Pll回路 Download PDFInfo
- Publication number
- JP5231931B2 JP5231931B2 JP2008264634A JP2008264634A JP5231931B2 JP 5231931 B2 JP5231931 B2 JP 5231931B2 JP 2008264634 A JP2008264634 A JP 2008264634A JP 2008264634 A JP2008264634 A JP 2008264634A JP 5231931 B2 JP5231931 B2 JP 5231931B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- unit
- input
- control value
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008264634A JP5231931B2 (ja) | 2008-10-10 | 2008-10-10 | Pll回路 |
| US12/560,395 US8085098B2 (en) | 2008-10-10 | 2009-09-15 | PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008264634A JP5231931B2 (ja) | 2008-10-10 | 2008-10-10 | Pll回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010093761A JP2010093761A (ja) | 2010-04-22 |
| JP2010093761A5 JP2010093761A5 (enExample) | 2011-11-10 |
| JP5231931B2 true JP5231931B2 (ja) | 2013-07-10 |
Family
ID=42256001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008264634A Expired - Fee Related JP5231931B2 (ja) | 2008-10-10 | 2008-10-10 | Pll回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5231931B2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11660075B2 (en) | 2016-12-16 | 2023-05-30 | Canon Medical Systems Corporation | Ultrasound diagnosis apparatus and ultrasound probe |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114257216B (zh) * | 2020-09-22 | 2026-04-21 | 深圳英集芯科技股份有限公司 | 一种两相三阶环形振荡器电路、相关芯片及电子装置 |
| CN117879593B (zh) * | 2023-12-14 | 2025-04-01 | 北京兆讯恒达技术有限公司 | 一种具有抗干扰功能的锁相环电路及相应的电子设备 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0823266A (ja) * | 1994-07-11 | 1996-01-23 | Mitsubishi Electric Corp | 電圧制御発振装置 |
| JP2944530B2 (ja) * | 1996-08-29 | 1999-09-06 | 山形日本電気株式会社 | 位相同期発振器 |
| US5942949A (en) * | 1997-10-14 | 1999-08-24 | Lucent Technologies Inc. | Self-calibrating phase-lock loop with auto-trim operations for selecting an appropriate oscillator operating curve |
| JP3254427B2 (ja) * | 1998-10-09 | 2002-02-04 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Vco特性のキャリブレーション方法 |
| JP2002111492A (ja) * | 2000-09-06 | 2002-04-12 | Internatl Business Mach Corp <Ibm> | 位相同期ループ用の自動較正システム |
| JP2002111450A (ja) * | 2000-09-29 | 2002-04-12 | Seiko Epson Corp | 電圧制御型発振回路 |
| JP3808338B2 (ja) * | 2001-08-30 | 2006-08-09 | 株式会社ルネサステクノロジ | 位相同期回路 |
| JP4866707B2 (ja) * | 2006-11-10 | 2012-02-01 | パナソニック株式会社 | Pll回路及び信号送受信システム |
-
2008
- 2008-10-10 JP JP2008264634A patent/JP5231931B2/ja not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11660075B2 (en) | 2016-12-16 | 2023-05-30 | Canon Medical Systems Corporation | Ultrasound diagnosis apparatus and ultrasound probe |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010093761A (ja) | 2010-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8085098B2 (en) | PLL circuit | |
| JP6121749B2 (ja) | フェーズロックドループ | |
| JP5448870B2 (ja) | Pll回路 | |
| CN107431488B (zh) | 锁相环(pll)架构 | |
| JP5515216B2 (ja) | フィードフォワード分割器を有する適応帯域幅位相ロックループ | |
| JP2010252289A (ja) | 電圧制御発振器のための補償回路 | |
| JP2001273725A (ja) | 位相同期ループ及び静止位相誤差制御方法 | |
| JP4593669B2 (ja) | バラツキ補正方法、pll回路及び半導体集積回路 | |
| US6667640B2 (en) | Phase locked loop circuit having a wide oscillation frequency range for reducing jitter | |
| JP2010093761A (ja) | Pll回路 | |
| US9391626B2 (en) | Capacitive load PLL with calibration loop | |
| JP2007184778A (ja) | リーク電流補償回路を備えたpll回路 | |
| KR100918860B1 (ko) | 루프필터 보상회로를 구비하는 주파수 합성기 | |
| JP5264401B2 (ja) | Pll回路 | |
| JP2003023354A (ja) | デジタル制御発振器 | |
| JP5338148B2 (ja) | 半導体集積回路、温度変化検出方法 | |
| JP4534140B2 (ja) | Pll回路 | |
| JP2009077308A (ja) | 位相ロックループ回路 | |
| US20060103476A1 (en) | Phase lock loop and the control method thereof | |
| US20090231003A1 (en) | Voltage controlled oscillator and pll and filter using the same | |
| JP2000036741A (ja) | Pll回路 | |
| JP2009200703A (ja) | チャージポンプ回路およびpll回路 | |
| US8373465B1 (en) | Electronic device and method for phase locked loop | |
| JP2012142814A (ja) | Pll回路 | |
| US7639091B2 (en) | Device for generation of a reference frequency and corresponding electronic circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110921 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110921 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130207 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130222 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130322 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160329 Year of fee payment: 3 |
|
| LAPS | Cancellation because of no payment of annual fees |