JP5231931B2 - PLL circuit - Google Patents

Description

  The present invention relates to a PLL circuit.

  2. Description of the Related Art In recent years, information recording apparatuses that write and read data to and from a recording medium such as an optical disk (for example, CD-R, DVD-R / RW) obtain a rotation synchronization signal of the recording medium and use the synchronization clock as a basis Is used as a recording clock during data recording processing. In general, a PLL (Phase Locked Loop) circuit is used to extract such a periodic clock.

  Patent Document 1 describes a VCO characteristic automatic variable PLL circuit as shown in FIG. In the PLL circuit, the phase comparator 2 compares the phases of the reference input inputted from the input terminal 1 and the output clock fed back from the frequency divider 6, and supplies the error signal to the DC amplifier 3. The DC amplifier 3 amplifies the supplied error signal and supplies it to the low-pass filter 4. The low-pass filter 4 filters an unnecessary frequency component from the supplied error signal and supplies it to the voltage controlled oscillator 11. The voltage controlled oscillator 11 oscillates an output clock having a frequency based on the selected VCO characteristic according to the supplied error signal, and supplies the output clock to the frequency divider 6. The frequency divider 6 divides the supplied output clock and outputs it from the output terminal 7 and feeds it back to the phase comparator 2.

  Here, as shown in FIG. 2 of Patent Document 1, the voltage controlled oscillator 11 in Patent Document 1 has a plurality of different VCO characteristics so as to satisfy a desired frequency range. Patent Document 1 describes selecting one of the plurality of VCO characteristics.

  Specifically, in the PLL circuit shown in FIG. 1 of Patent Document 1, the upper limit voltage comparator 15 and the lower limit voltage comparator 16 show that the error signal filtered by the low-pass filter 4 is shown in FIG. A comparison is made to determine whether the voltage is within the range from the upper limit voltage to the lower limit voltage. The upper limit voltage comparator 15 and the lower limit voltage comparator 16 supply the determination signal to the VCO characteristic switch 17. The VCO characteristic switching unit 17 does not switch the VCO characteristic when the error signal is a point A within the range from the upper limit voltage to the lower limit voltage shown in FIG. When the error signal is a point B equal to or higher than the upper limit voltage shown in FIG. 2 of Patent Document 1, the VCO characteristic switcher 17 switches to the VCO characteristic having a higher oscillation frequency with respect to the control voltage than the selected VCO characteristic. When the error signal is a point D that is equal to or lower than the lower limit voltage shown in FIG. 2 of Patent Document 1, the VCO characteristic switcher 17 switches to a VCO characteristic having a lower oscillation frequency with respect to the control voltage than the selected VCO characteristic.

  Thus, according to Patent Document 1, it is possible to automatically switch to the optimum VCO characteristic according to the error signal.

Further, in Patent Document 2, as shown in FIG. 3 of Patent Document 2, a charge pump phase lock loop 300 is described. In this charge pump phase-locked loop 300, during a normal PLL operation, the phase / frequency detector (PFD) 302 compares the phase of the input signal _{FIN with} the phase of the feedback signal _FFB . The PFD 302 generates an error signal of either the up signal U or the down signal D according to the comparison result and supplies the error signal to the charge pump 304. The charge pump 304 charges the capacitor of the loop filter 306 or removes the charge from the capacitor depending on whether the error signal is an up signal or a down signal, and generates a loop filter voltage V _LF . The loop filter 306 supplies the loop filter voltage V _LF to the voltage controlled oscillator 308 via the turned-on switch SW1. The voltage controlled oscillator 308 generates and outputs an internal signal F _OSC determined by the selected VCO operation curve for the supplied loop filter voltage V _LF .

  Here, the voltage controlled oscillator 308 shown in FIG. 3 of Patent Document 2 has many VCO operations as shown in FIG. 2 of FIG. 2 of Patent Document 2, like the voltage controlled oscillator 108 shown in FIG. It has a curve. Patent Document 2 describes that one VCO operation curve among many VCO operation curves is selected (trimmed) using a special digital control input value N.

Specifically, in the charge pump phase-locked loop 300 shown in FIG. 3 of Patent Document 2, the switch SW1 is open and the switch SW2 is closed during automatic trimming. A reference voltage V _REF is supplied to the voltage controlled oscillator 308 instead of the loop filter voltage V _LF . Charge pump 304 provides loop filter voltage V _LF to state machine 316. The state machine 316 sequentially selects different VCO operating curves by sequentially selecting the digital control input value N and supplying it to the voltage controlled oscillator 308. The state machine 316 detects that the loop filter voltage V _LF has converged to an appropriate quiescent voltage (either ground or V _DD ). This causes the state machine 316 to identify two VCO operating curves having a center frequency just above and below the frequency of the input signal _FIN , and one of the two identified VCO operating curves to be used for normal PLL operation. Select for use sometimes.

Thus, according to Patent Document 2, an appropriate VCO operation curve can be automatically selected.
JP 2000-4156 A Japanese Patent Laid-Open No. 11-195983

  Here, a PLL circuit including a phase comparator, a charge pump circuit, a low-pass filter, a voltage controlled oscillator (VCO circuit), and a frequency divider circuit is considered. The loop characteristics of the PLL circuit are determined by the gain characteristics and frequency characteristics of the circuit to be configured, and by appropriately designing them, characteristics such as a lock-in time and a jitter until the phase is locked are made desirable. Regarding the gain characteristic in the PLL characteristic, the gain characteristic of the VCO circuit is particularly dominant.

  The gain characteristic (control voltage-oscillation frequency characteristic) of the VCO circuit varies due to variations in power supply voltage and manufacturing process. When the VCO circuit has a high gain, the fluctuation of the oscillation frequency due to the external noise superimposed on the control voltage input to the VCO circuit increases, and the jitter increases. Further, when the VCO circuit has a low gain, the oscillation frequency of the signal output from the VCO circuit may not reach a desired frequency even with the upper limit value of the control voltage setting range determined by the power supply voltage and the circuit configuration. As described above, if the gain of the VCO circuit varies with respect to the design value, the jitter may increase or the lock-in time may increase, and the PLL characteristics may not be desired.

  In Patent Document 1, as shown in FIGS. 8 and 9 of Patent Document 1, gain variation in a range between an upper limit voltage and a lower limit voltage in a desired frequency range with respect to a control voltage to the VCO circuit at the time of locking. Is acceptable. As a result, there is a possibility that the gain of the corrected VCO circuit remains with some variation and the PLL characteristic does not become a desired characteristic.

  Patent Document 2 describes selecting one VCO operation curve among many VCO operation curves as described above. Of the many VCO operation curves prepared in advance, there may be no VCO operation curve corresponding to a desired PLL characteristic due to variations in gain characteristics. In this case, even if one VCO operation curve among many VCO operation curves is selected, the PLL characteristic may not be a desired characteristic.

Patent Document 2 describes that, among many operation curves, one operation curve is selected such that the loop filter voltage V _LF converges to a static voltage (either ground or V _DD ). . In this case, the voltage controlled oscillator 308 of Patent Document 2 is supplied with a voltage different from that at the time of automatic trimming during normal PLL operation after the automatic trimming is performed, so that the PLL circuit may not operate with desired characteristics. There is sex.

  An object of the present invention is to make a PLL response characteristic in a PLL circuit a desired characteristic according to a reference voltage.

  A PLL circuit according to one aspect of the present invention includes an oscillation unit that generates an internal signal by oscillating at a frequency according to an input voltage, and a frequency divider that generates a divided signal by dividing the internal signal. A phase comparison unit that compares the phase of the reference signal input from the outside with the phase of the frequency division signal received from the frequency division unit, and outputs a phase error signal according to the comparison result; A PLL circuit having a generation unit that generates a control voltage based on an error signal, wherein the control voltage output from the generation unit is input to the oscillation unit, and a reference voltage is A switching unit that switches between a second state input to the oscillation unit, and the control voltage output from the generation unit in the second state is compared with the reference voltage and output from the generation unit The control voltage is equal to the reference voltage So as to, characterized in that a correcting unit for correcting the frequency oscillated in the oscillation portion with respect to the voltage input to the oscillating unit.

  According to the present invention, the PLL response characteristic in the PLL circuit can be set to a desired characteristic according to the reference voltage.

  A PLL (Phase Locked Loop) circuit 100 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a configuration of a PLL circuit 100 according to the first embodiment of the present invention.

  The PLL circuit 100 generates an internal signal oclk having a specific phase relationship with respect to a reference signal rclk input from the outside. The PLL circuit 100 includes a frequency dividing unit 60, a phase comparison unit 10, a generation unit 20, a switching unit 40, an oscillation unit 30, and a correction unit 50.

  The frequency divider 60 divides the internal signal oclk to generate a frequency-divided signal iclk. The frequency dividing unit 60 includes a frequency dividing circuit 107. The frequency dividing circuit 107 divides the internal signal oclk by a predetermined number of divisions, generates a divided signal iclk, and feeds it back to the phase comparison unit 10.

  The phase comparator 10 compares the phase of the reference signal rclk received from the outside with the phase of the divided signal iclk received from the divider 60 and outputs a phase error signal corresponding to the comparison result. The phase comparison unit 10 includes a phase comparator (PC) 101. The phase comparator 101 outputs a phase error signal corresponding to the phase difference between the reference signal rclk and the divided signal iclk to the generation unit 20.

  The generation unit 20 generates a control voltage based on the phase error signal. The generation unit 20 includes a charge pump circuit (CP) 102 and a low pass filter (LPF) 103.

  The charge pump circuit 102 receives the phase error signal output from the phase comparator 101. The charge pump circuit 102 includes a capacitor, and generates a charge pump current by charging or discharging the capacitor based on the phase error signal. The charge pump circuit 102 outputs the generated charge pump current to the low pass filter 103.

  The low pass filter 103 receives the charge pump current output from the charge pump circuit 102. The low-pass filter 103 generates the control voltage Vcnt by smoothing the received charge pump current. The low-pass filter 103 outputs the generated control voltage Vcnt to the switching unit 40 and the correction unit 50.

  The switching unit 40 switches between a first state in which the control voltage Vcnt output from the generation unit 20 is input to the oscillation unit 30 and a second state in which the reference voltage Vref is input to the oscillation unit 30. The switching unit 40 includes a first control switch 104 and a second control switch 105.

  The first control switch 104 turns on and off the conduction between the generation unit 20 and the oscillation unit 30. The second control switch 105 turns on / off the conduction between the reference voltage Vref and the oscillation unit 30. Accordingly, the switching unit 40 switches to the first state by turning on the first control switch 104 (into a conductive state) and turning off the second control switch 105 (into a non-conductive state). The switching unit 40 switches to the second state by turning off the first control switch 104 (in a non-conducting state) and turning on the second control switch 105 (in a conducting state).

  The oscillation unit 30 generates an internal signal oclk by oscillating at a frequency fo corresponding to the input voltage. The oscillation unit 30 includes a voltage controlled oscillator 106.

  The voltage controlled oscillator 106 receives the reference voltage Vref when switched to the second state by the switching unit 40. The voltage controlled oscillator 106 generates an internal signal oclk by oscillating at a frequency fo (see FIG. 2) corresponding to the received reference voltage Vref. Voltage controlled oscillator 106 outputs internal signal oclk to frequency divider 60.

  The correction unit 50 corrects the gain of the oscillation unit 30 so that the control voltage Vcnt output from the generation unit 20 becomes equal to the reference voltage Vref when the switching unit 40 switches to the second state. Here, the gain is a characteristic of the frequency at which the oscillation unit 30 oscillates with respect to the voltage input to the oscillation unit 30. The correction unit 50 includes a gain correction circuit 110.

  The gain correction circuit 110 continuously corrects the gain of the oscillating unit 30 by comparing the control voltage Vcnt output from the generation unit 20 with the reference voltage Vref.

  Specifically, the gain correction circuit 110 corrects the gain of the oscillating unit 30 so that the gain of the oscillating unit 30 decreases when the control voltage Vcnt is lower than the reference voltage Vref. That is, the gain correction circuit 110 corrects the gain of the oscillating unit 30 so that the gain of the oscillating unit 30 decreases when the oscillation frequency fo of the oscillating unit 30 is higher than a reference value (for example, fh> ft shown in FIG. 2). To do.

  The gain correction circuit 110 corrects the gain of the oscillating unit 30 so that the gain of the oscillating unit 30 increases when the control voltage Vcnt is higher than the reference voltage Vref. That is, the gain correction circuit 110 corrects the gain of the oscillating unit 30 so that the gain of the oscillating unit 30 increases when the oscillation frequency fo of the oscillating unit 30 is lower than the reference value (for example, fl <ft shown in FIG. 2). To do.

  The voltage controlled oscillator 106 receives the control voltage Vcnt output from the generation unit 20 when the switching unit 40 switches to the first state. The voltage controlled oscillator 106 generates an internal signal oclk by oscillating at a frequency fo corresponding to the received control voltage Vcnt in a state where the gain is corrected. The voltage controlled oscillator 106 outputs the internal signal oclk to the outside and outputs it to the frequency dividing unit 60.

  In this way, the gain of the voltage controlled oscillator 106 is continuously corrected so that the control voltage Vcnt output from the generation unit 20 becomes equal to the reference voltage Vref. Thereby, in the second state, the gain characteristic of the voltage controlled oscillator 106 can be set to a desired characteristic corresponding to the reference voltage Vref.

  Further, the voltage controlled oscillator 106 generates the internal signal oclk for outputting the control voltage Vcnt having a value equal to the reference voltage Vref from the generation unit 20 in a state where the reference voltage Vref is input in the second state. The gain is corrected. Thereby, in the first state after the gain correction of the voltage controlled oscillator 106 in the second state is performed, the same voltage as that in the second state can be input to the voltage controlled oscillator 106. As a result, in the state after correction, the PLL circuit operates with desired characteristics corresponding to the reference voltage Vref.

  That is, the PLL characteristic in the PLL circuit can be set to a desired characteristic corresponding to the reference voltage. Note that the PLL operation means that feedback control is performed so that the frequency and phase of the frequency-divided signal iclk generated by the frequency division unit 60 match the frequency and phase of the reference signal rclk.

  Next, the gain correction operation by the gain correction circuit 110 will be described with reference to FIG. FIG. 2 is a diagram illustrating an example of the gain characteristic of the frequency fo of the internal signal oclk with respect to the control voltage Vcnt of the voltage controlled oscillator 106. Here, the gain is represented by the slope of a straight line indicating the frequency characteristic in FIG.

  FIG. 2 shows that the oscillation frequency becomes the reference value ft when the control voltage Vcnt is equal to the reference voltage Vref when the gain of the voltage controlled oscillator 106 is a TYP (standard) condition. Here, the TYP condition is a case where the power supply voltage is a standard value and the characteristics of the constituent elements of the voltage controlled oscillator 106 that vary due to variations in the manufacturing process are standard. The reference value ft is a frequency obtained by multiplying the frequency of the ideal reference signal rclk by the frequency dividing number of the frequency dividing circuit 107. Here, when the gain of the voltage controlled oscillator 106 is high due to power supply voltage fluctuation or manufacturing process variation, when the reference voltage Vref is input to the voltage controlled oscillator 106, the oscillation frequency becomes fh higher than the reference value ft. . Similarly, when the gain is low, when the reference voltage Vref is input to the voltage controlled oscillator 106, the oscillation frequency becomes fl lower than the reference value ft.

  The PLL circuit according to the present embodiment causes the gain variation of the voltage controlled oscillator 106 to deviate from the gain characteristic under the TYP condition so that the gain characteristic under the TYP condition is obtained by the gain correction signal from the gain correction circuit 110. It is to correct.

  When this gain correction operation is performed, the first control switch 104 is turned off and the second control switch 105 is turned on. Therefore, the reference voltage Vref is input to the voltage controlled oscillator 106 and an oscillation frequency determined by the gain characteristic of the voltage controlled oscillator 106 is output.

  Here, when the gain characteristic is higher than the TYP condition, the oscillation frequency becomes fh higher than the reference value ft. Therefore, the control voltage Vcnt of the low-pass filter 103 is raised so as to approach the reference voltage Vref from a value lower than the reference voltage Vref by performing an operation to lower the oscillation frequency by the gain correction circuit 110.

  On the other hand, when the gain characteristic is lower than the TYP condition, the oscillation frequency becomes fl lower than the reference value ft. For this reason, the control voltage Vcnt of the low-pass filter 103 is lowered so as to approach the reference voltage Vref from a value higher than the reference voltage Vref by performing an operation to increase the oscillation frequency by the gain correction circuit 110.

  As described above, the gain correction circuit 110 compares the control voltage Vcnt output from the low-pass filter 103 with the reference voltage Vref and performs gain correction of the voltage controlled oscillator 106 according to the difference between the two. This gain correction operation is performed by the gain correction circuit 110 until the difference between the control voltage Vcnt and the reference voltage Vref disappears, so that the gain of the voltage controlled oscillator 106 can be matched with that at the time of TYP.

  After performing this gain correction operation, the first control switch 104 is turned on, the second control switch 105 is turned off, and the normal PLL circuit operation is performed by the voltage controlled oscillator 106 having a gain at the time of TYP. Is possible.

  In the PLL circuit of this embodiment, the lock-in time can be shortened even if a gain correction period is provided. Here, before starting the gain correction operation by starting the circuit, the first control switch 104 and the second control switch 105 are turned on. Thereby, the reference voltage Vref can be applied as the initial voltage to the control voltage Vcnt of the low-pass filter 103 before the gain correction operation is started.

  If this initial voltage is not given, the control voltage Vcnt rises slowly, for example, from the GND potential with the time constant set by the low-pass filter 103, so that this voltage becomes close to the Vref voltage. It takes a lot of time.

  On the other hand, in this embodiment, the Vref voltage is given as the initial voltage, so that the time required for rising from the GND potential to the Vref voltage can be shortened.

  Therefore, in this embodiment, even when the gain of the voltage controlled oscillator fluctuates due to variations in the power supply voltage and the manufacturing process, a desired PLL response characteristic can be obtained by performing gain correction, and a stable PLL loop characteristic can be obtained. Can be obtained. Even if a gain correction period is provided, the lock-in time can be shortened.

  A PLL circuit 100i according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing a configuration of a PLL circuit 100i according to the second embodiment of the present invention. Below, it demonstrates centering on a different part from 1st Embodiment.

  The PLL circuit 100i includes an oscillation unit 30i and a correction unit 50i.

  The oscillation unit 30i includes a voltage controlled oscillator 106i. The voltage controlled oscillator 106i includes an NMOS transistor 1065i, a load element 1066i, a ring oscillator 1062i, a current mirror circuit 1063i, and a current mirror circuit 1064i.

  In the NMOS transistor 1065i (input transistor), the control voltage Vcnt output from the generation unit 20 in the first state is input to the gate, and the reference voltage Vref is input to the gate in the second state. The NMOS transistor 1065i performs a source follower operation together with the load element 1066i and a MOS transistor 115 described later, thereby causing a drain current for determining a predetermined gain with respect to the voltage input to the gate to flow between the source and the drain.

  This drain current is turned back and supplied to the ring oscillator 1062i by a current mirror circuit 1063i formed of a PMOS transistor and a current mirror circuit 1064i formed of an NMOS transistor. That is, each of the current mirror circuit 1063i and the current mirror circuit 1064i passes a current corresponding to the current flowing through the drain of the NMOS transistor 1065i.

  The ring oscillator 1062i is formed by connecting inverters in odd stages in cascade (in the case of three stages in the drawing). The ring oscillator 1062i receives the current passed by the current mirror circuit 1063i and the current mirror circuit 1064i, and oscillates at a frequency corresponding to the magnitude of the received current. In the ring oscillator 1062i, the oscillation frequency is controlled by the magnitude of the drive current supplied to each inverter.

  That is, the source 1061i of the NMOS transistor 1065i determines the ratio of the oscillation frequency of the ring oscillator 1062i to the control voltage Vcnt input to the gate of the NMOS transistor 1065i, depending on the magnitude of the drain current that flows. That is, the source 1061i of the NMOS transistor 1065i determines the gain of the oscillation unit 30i according to the magnitude of the drain current that flows. Specifically, the source 1061i of the NMOS transistor 1065i is connected to the load element 1066i. The gain of the oscillating unit 30i decreases as the magnitude of current flowing through the source 1061i of the NMOS transistor 1065i decreases, and increases as the magnitude of current flowing through the source 1061i of the NMOS transistor 1065i increases.

  The correction unit 50i includes a gain correction circuit 110i. The gain correction circuit 110i includes a comparator (voltage comparison unit) 111, a flip-flop (holding unit) 112, an up / down counter (control value holding unit) 113, a D / A converter (DAC, D / A conversion unit) 114, In addition, a MOS transistor 115 is included.

  The comparator 111 receives the control voltage Vcnt of the low-pass filter 103 and the reference voltage Vref. The comparator 111 outputs a high level when the control voltage Vcnt is higher than the reference voltage Vref, and outputs a low level when the control voltage Vcnt is low. That is, the comparator 111 compares the control voltage Vcnt received from the generation unit 20 with the reference voltage Vref and outputs a voltage error signal according to the comparison result.

  The flip-flop 112 receives the voltage error signal output from the comparator 111 and temporarily holds (stores) the voltage error signal in synchronization with the reference clock clock.

  The up / down counter 113 changes the held digital control value in accordance with the voltage error signal output from the flip-flop 112 and holds the changed digital control value. In the initial state, the up / down counter 113 holds an initial digital control value.

  Specifically, the up / down counter 113 holds digital control when the voltage error signal indicates that the control voltage Vcnt is higher than the reference voltage Vref, that is, when the voltage error signal is at a high level. Count up the value. The up / down counter 113 holds the counted digital control value.

  The up / down counter 113 counts down the held digital control value when the voltage error signal indicates that the control voltage Vcnt is lower than the reference voltage Vref, that is, when the voltage error signal is at a low level. To do. The up / down counter 113 holds the digital control value counted down.

  The D / A converter 114 receives the changed digital control value from the up / down counter 113. The D / A converter 114 D / A converts the received digital control value to generate an analog control value.

  In the MOS transistor 115, the analog control value output from the D / A converter 114 is input to the gate, the source is connected to the ground voltage, and the drain is connected to the source 1061i of the NMOS transistor 1065i.

  Specifically, when an analog control value corresponding to the counted-up digital control value is input to the gate of the MOS transistor 115, its equivalent resistance value is lowered, that is, its mutual conductance gm is increased ( Increase). Thereby, the MOS transistor 115 increases the magnitude of the current flowing through the source 1061i of the NMOS transistor 1065i.

  In addition, when an analog control value corresponding to the counted-down digital control value is input to the gate of the MOS transistor 115, its equivalent resistance value increases, that is, its mutual conductance gm decreases (decreases). As a result, the MOS transistor 115 reduces the magnitude of the current flowing through the source 1061i of the NMOS transistor 1065i.

  Meanwhile, the mutual conductance gm of the NMOS transistor 1065i can be continuously controlled by an analog voltage input to the gate terminal thereof, but the analog control value output from the D / A converter 114 is a discrete value. Therefore, by sufficiently increasing the resolution of the D / A converter 114, the gain of the voltage controlled oscillator 106i can be continuously controlled to such an extent that it does not cause a practical problem.

  Next, the operation in the case where the gain of the voltage controlled oscillator 106i in the gain correction operation is TYP (gain: TYP shown in FIG. 2) will be described.

  When this gain correction operation is performed, the first control switch 104 is turned off and the second control switch 105 is turned on. Here, the up / down counter 113 outputs an initial digital control value to the D / A converter 114. The D / A converter 114 generates an initial analog control value by performing D / A conversion on the initial digital control value. As a result, a voltage corresponding to the initial analog control value is input to the gate of the MOS transistor 115 for gain correction. As a result, the gm value of the MOS transistor 115 for gain correction becomes a fixed value (initial value), and the initial gain of the voltage controlled oscillator 106i is set by this gm value and the resistance value of the load element 1066i. This initial gain is set so that the oscillation frequency becomes ft when the reference voltage Vref is input to the voltage controlled oscillator 106i under the TYP condition. Since the control voltage Vcnt of the low-pass filter 103 substantially matches the reference voltage Vref when the gain is TYP, the output of the comparator 111 repeats the high level and the low level at the same rate. Therefore, the up / down counter 113 repeats count-up and count-down using the initial value as the center value, and when averaged, it becomes the same value as the initial value. For this reason, the gain of the voltage controlled oscillator 106i does not change from the initial gain.

  Next, an operation when the gain of the voltage controlled oscillator 106i in the gain correction operation is higher than that at the time of TYP (gain shown in FIG. 2: HIGH) will be described.

  Here, since the reference voltage Vref is input to the voltage controlled oscillator 106i, the oscillation frequency becomes fh higher than the reference value ft (see FIG. 2). At this time, the control voltage Vcnt output from the low pass filter 103 is lower than the reference voltage Vref. As a result, the comparator 111 outputs a low level to the flip-flop 112. The flip-flop 112 outputs a low level to the up / down counter 113 in synchronization with the reference clock clock. Therefore, the up / down counter 113 counts down the held digital control value (for example, the initial digital control value). Thereafter, the D / A converter 114 converts the count value of the up / down counter 113 at an appropriate timing. At this time, since the gate voltage of the MOS transistor 115 for gain correction becomes lower than the initial voltage value, the gm value becomes smaller. Here, the gain of the voltage controlled oscillator 106i is set by a parallel resistance value of the bias current setting resistance value and the gm value. This parallel resistance value increases, and as a result, the gain of the voltage controlled oscillator 106i decreases. Therefore, the oscillation frequency of the voltage controlled oscillator 106i is lowered, and the control voltage Vcnt approaches the reference voltage Vref. By repeating this operation, the control voltage Vcnt is matched with the reference voltage Vref, and the gain can be matched with that at the time of TYP.

  Next, the operation when the gain of the voltage controlled oscillator 106i in the gain correction operation is lower than that at the time of TYP (the gain shown in FIG. 2 is LOW) will be described.

  Here, the oscillation frequency is fl lower than the reference value ft. At this time, the control voltage Vcnt is higher than the reference voltage Vref. As a result, the comparator 111 outputs a high level, and the flip-flop 112 outputs a high level in synchronization with the reference clock clock. Therefore, the up / down counter 113 counts up the held digital control value (for example, the initial digital control value). The gate voltage of the MOS transistor 115 for gain correction after D / A conversion becomes higher than the initial voltage value. As a result, the gm value of the MOS transistor 115 is increased, and the gain of the voltage controlled oscillator 106i is increased. By repeating this operation, the gain can be adjusted to that at the time of TYP.

  Next, a PLL circuit 100j according to a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram showing a configuration of a PLL circuit 100j according to the third embodiment of the present invention. Below, it demonstrates centering on a different part from 2nd Embodiment.

  The PLL circuit 100j includes a correction unit 50j.

  The correction unit 50j includes a gain correction circuit 110j. The gain correction circuit 110j includes an operational amplifier (differential amplification unit) 121, a storage capacitor (holding unit) 122, an A / D converter (A / D conversion unit) 123, a D / A converter 124, and a MOS transistor 125. .

  In the operational amplifier 121, the control voltage Vcnt output from the low-pass filter 103 is input to the positive input terminal, and the reference voltage Vref is input to the negative input terminal. Here, the operational amplifier 121 is a transconductance amplifier that outputs a current with respect to an input differential voltage. A storage capacitor 122 is connected to the output terminal of the operational amplifier 121. Accordingly, the operational amplifier 121 generates a differential signal between the control voltage Vcnt received from the generation unit 20 and the reference voltage Vref and outputs the differential signal to the storage capacitor 122.

  Specifically, the operational amplifier 121 discharges current when a differential signal indicating that the control voltage Vcnt is higher than the reference voltage Vref, and increases the differential voltage held by the storage capacitor 122 to increase the differential voltage. The held differential voltage is held in the holding capacitor 122.

  Further, the operational amplifier 121 absorbs current when a differential signal indicating that the control voltage Vcnt is lower than the reference voltage Vref is output, and reduces the differential voltage held by the holding capacitor 122 to reduce the difference. The dynamic voltage is held in the holding capacitor 122.

  The holding capacitor 122 temporarily holds a differential voltage corresponding to the differential signal output from the operational amplifier 121. The holding capacitor 122 has a capacitance value Co, and generates and holds a differential voltage determined from the capacitance value Co for the received differential signal.

  The A / D converter 123 A / D converts the differential voltage held by the holding capacitor 122 to generate a digital control value.

  The D / A converter 124 generates an analog control value by D / A converting the digital control value generated by the A / D converter 123.

  In the MOS transistor 125, the analog control value output from the D / A converter 124 is input to the gate, the source is connected to the ground voltage, and the drain is connected to the source 1061i of the NMOS transistor 1065i.

  Specifically, when an analog control value corresponding to the increased differential voltage is input to the gate of the MOS transistor 125, its equivalent resistance value is lowered, that is, its mutual conductance gm is increased. Thereby, the MOS transistor 115 increases the magnitude of the current flowing through the source 1061i of the NMOS transistor 1065i.

  In addition, when an analog control value corresponding to the reduced differential voltage is input to the gate of the MOS transistor 115, its equivalent resistance value increases, that is, its mutual conductance gm decreases. As a result, the MOS transistor 115 reduces the magnitude of the current flowing through the source 1061i of the NMOS transistor 1065i.

  Further, the gain correction operation is different from the second embodiment in the following points.

  In the operation when the gain of the voltage controlled oscillator 106 in the correction operation is TYP, the operational amplifier 121 performs the following operation. The operational amplifier 121 does not output current when the control voltage Vcnt and the reference voltage Vref have the same voltage value. As a result, the voltage value of the storage capacitor 122 becomes the initial value Vco. Based on this voltage value, the gain of the voltage controlled oscillator 106 under the TYP condition is set.

  In the operation when the gain of the voltage controlled oscillator 106 in the correction operation is higher than that in TYP, the reference voltage Vref is input to the voltage controlled oscillator 106. For this reason, the oscillation frequency is fh higher than the reference value ft. At this time, the control voltage Vcnt is lower than the reference voltage Vref. As a result, the operational amplifier 121 sinks current, and the voltage value of the storage capacitor 122 decreases from the initial value Vco. Thereafter, at an appropriate timing, the voltage value of the storage capacitor 122 is A / D converted by the A / D converter 123, and this output signal is D / A converted by the D / A converter 124. At this time, since the gate voltage of the MOS transistor 125 for gain correction becomes lower than the initial voltage value, the gm value becomes smaller. As a result, the gain of the voltage controlled oscillator 106 decreases. Therefore, the oscillation frequency of the voltage controlled oscillator 106 is lowered, and the control voltage Vcnt approaches the reference voltage Vref. By repeating this operation, the control voltage Vcnt is matched with the reference voltage Vref, and the gain can be matched with that at the time of TYP.

  In the operation when the gain of the voltage controlled oscillator 106 in the correction operation is lower than that in TYP, the oscillation frequency becomes fl lower than the reference value ft. At this time, the control voltage Vcnt is higher than the reference voltage Vref. As a result, the operational amplifier 121 discharges current, the voltage value of the storage capacitor 122 rises from the Vco voltage, and the gate voltage of the gain correcting NMOS transistor after D / A conversion becomes higher than the initial voltage value. As a result, the gm value increases and the gain of the voltage controlled oscillator 106 increases. By repeating this operation, the gain can be adjusted to that at the time of TYP.

  In the description of the above embodiment, a description is given of a case where the gain correction operation is performed only once at the start-up, and then the normal PLL circuit operation is performed thereafter. However, the gain correction operation is not limited to one time. For example, a correction period may be provided every time the operation from the standby state is started, or a correction period may be provided in a period in which the phase lock of the PLL circuit is unnecessary.

  In the description of the above embodiment, the gain correction is performed by controlling the inverter drive current of the ring oscillator constituting the voltage controlled oscillator. However, any gain correction method may be used, such as performing gain correction by controlling the power supply voltage of the ring oscillator circuit based on the difference between the output voltage from the low-pass filter and the reference voltage.

  In the description of the above embodiment, the voltage controlled oscillator is configured by a ring oscillator, but the voltage controlled oscillator may have any circuit configuration.

  In the description of the above embodiment, the reference signal rclk is the same signal during gain correction operation and normal PLL circuit operation. However, in order to prevent the reference signal from fluctuating during the gain correction operation, for example, the correction is performed by inputting the oscillation frequency of the crystal resonator, and the reference signal to be locked is input during the normal PLL circuit operation. rclk may be switched according to the operating state.

1 is a diagram showing a configuration of a PLL circuit 100 according to a first embodiment of the present invention. The figure which shows the gain characteristic of the voltage controlled oscillator in 1st Embodiment of this invention. The figure which shows the structure of the PLL circuit 100i which concerns on 2nd Embodiment of this invention. The figure which shows the structure of PLL circuit 100j which concerns on 3rd Embodiment of this invention.

Explanation of symbols

100, 100i, 100j PLL circuit

Claims (7)

An oscillation unit that generates an internal signal by oscillating at a frequency according to the input voltage, a frequency dividing unit that divides the internal signal to generate a divided signal, and a reference signal input from the outside A PLL circuit having a phase comparison unit that compares a phase with the phase of the frequency-divided signal and outputs a phase error signal according to a comparison result, and a generation unit that generates a control voltage based on the phase error signal. There,
A switching unit that switches between a first state in which the control voltage is input to the oscillation unit and a second state in which a reference voltage is input to the oscillation unit;
In the second state, the control voltage is compared with the reference voltage, and the oscillation frequency in the oscillation unit is corrected with respect to the voltage input to the oscillation unit so that the control voltage becomes equal to the reference voltage. And a correction unit that
The correction unit corrects a gain of the oscillation unit that is a characteristic of an oscillation frequency in the oscillation unit with respect to a voltage input to the oscillation unit, so that the control voltage becomes equal to the reference voltage,
The oscillation unit is
An input transistor to which the control voltage or the reference voltage is input to a gate;
A current mirror circuit for passing a current according to a current flowing between the source and drain of the input transistor;
A ring oscillator that receives a current passed by the current mirror circuit and oscillates at a frequency according to the magnitude of the received current,
The correction unit includes a MOS transistor whose mutual conductance is controlled based on a comparison result between the control voltage and the reference voltage,
When the control voltage is higher than the reference voltage, the transconductance of the MOS transistor decreases, and when the control voltage is lower than the reference voltage, the transconductance of the MOS transistor increases.
The correction unit is
Comparing the reference voltage with the previous SL control voltage, a voltage comparison unit for outputting a voltage error signal corresponding to the comparison result,
A holding unit that temporarily holds the previous SL voltage error signal,
A control value holding unit that changes the held digital control value according to the voltage error signal temporarily held in the holding unit and output from the holding unit, and holds the changed digital control value; ,
A D / A converter that generates an analog control value by D / A converting the changed digital control value held in the control value holding unit and output from the control value holding unit;
The analog control value is input to a gate, a source connected to a ground voltage, a drain PLL circuit you comprising the, said MOS transistor connected to the source of the input transistor. When the voltage error signal indicates that the control voltage is higher than the reference voltage, the control value holding unit counts up the held digital control value and outputs the counted up digital control value. If the voltage error signal indicates that the control voltage is lower than the reference voltage, count down the held digital control value, hold the counted down digital control value,
When the analog control value corresponding to the counted-up digital control value is input to the gate, the MOS transistor increases the magnitude of the current flowing between the source and drain of the input transistor, and the counted-down digital control value When an analog control value corresponding to the control value is input to the gate, the magnitude of the current flowing between the source and drain of the input transistor is reduced,
The gain of the oscillating unit increases as the current flowing between the source and drain of the input transistor increases, and decreases as the current flowing between the source and drain of the input transistor decreases. The PLL circuit according to claim 1 . The correction unit is
A differential amplifier for generating and outputting a differential signal of the previous SL control voltage and the reference voltage,
A holding unit for temporarily holding the differential voltage corresponding to the prior SL differential signal,
An A / D converter that A / D converts the differential voltage held by the holding unit to generate a digital control value;
A D / A converter that generates an analog control value by D / A converting the digital control value;
Is input before Symbol analog control value to the gate, a source connected to a ground voltage, a drain PLL circuit according to claim 1, characterized in that it comprises, said MOS transistor connected to the source of the input transistor . When the differential amplification unit outputs the differential signal indicating that the control voltage is higher than the reference voltage, the differential amplification unit increases the differential voltage held by the holding unit and increases the differential voltage. Is held by the holding unit, and the differential signal indicating that the control voltage is lower than the reference voltage is output, the differential voltage held by the holding unit is decreased, and the reduced differential Holding the voltage in the holding unit,
When the analog control value corresponding to the increased differential voltage is input to the gate, the MOS transistor increases the amount of current flowing between the source and the drain of the input transistor, and reduces the decreased differential. When an analog control value corresponding to the voltage is input to the gate, the magnitude of the current flowing between the source and drain of the input transistor is reduced,
The gain of the oscillating unit increases as the current flowing between the source and drain of the input transistor increases, and decreases as the current flowing between the source and drain of the input transistor decreases. The PLL circuit according to claim 3 . The generator is
A charge pump circuit including a capacitor and generating a charge pump current by charging or discharging the capacitor based on the phase error signal;
A low-pass filter that generates the control voltage by smoothing the charge pump current output from the charge pump circuit;
PLL circuit according to claim 1, any one of 4, which comprises a. The switching unit is
A first control switch for switching conduction between the generation unit and the oscillation unit;
A second control switch for switching conduction between the reference voltage and the oscillation unit;
Including
In the first state, the first control switch is turned on and the second control switch is turned off.
The PLL according to any one of claims 1 to 5 , wherein, in the second state, the first control switch is turned off and the second control switch is turned on. circuit. PLL circuit according to any one of claims 1 6, characterized in that the said second state upon activation of the PLL circuit.

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