JP2002111450A - Voltage controlled oscillating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve low voltage operation of a voltage controlled oscillating circuit. SOLUTION: Controlling transistors TC1 to TC3 comprising N-channel MOS transistors are connected between a connecting point between drains of both transistors constituting CMOS inverters IN1 to IN3 and grounding potential, and a control voltage VC is applied to gates of the TC1 to TC3. By this, a controlling current Id is made to flow through the TC1 to TC3, which results in varying the inverter current If flowing through the IN1 to IN3, and oscillation frequencies of oscillation output varies. Since the TC1 to TC3 are connected between the connecting point between the drains of both transistors constituting the IN1 to IN3 and grounding potential, the low voltage operation can be achieved as compared when the T1 to TC3 are connected in series with the IN1 to IN3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-controlled oscillation circuit, and more particularly to a voltage-controlled oscillation circuit capable of reducing its voltage.

[0002]

2. Description of the Related Art As a conventional voltage controlled oscillation circuit, for example, a circuit having a configuration shown in FIG. 5 is known.

[0003] This voltage controlled oscillation circuit has a P-channel M
Three sets of CMOS inverters IN _{1 to} IN ₃ configured by connecting the OS field-effect transistor TR _P and the N-channel MOS field-effect transistor TR _N in series are ring-connected. That is, the first-stage CMOS inverter I
The connection point between the drains of both transistors TR _P and TR _N of N ₁ is connected to the gates of both transistors TR _P and TR _N of the next-stage CMOS inverter IN ₂ , and similarly, both transistors TR _P of the CMOS inverter IN ₂
And TR connection point between the drain of the _N is the final stage CM
Both transistors TR _P and TR of OS inverter IN _{3
N 3} connected to the gate of the CMOS inverter IN ₃
Connection point between the transistors TR _P and TR _N is connected to the gates of the transistors TR _P and TR _N of the first-stage CMOS inverter IN _1, the last stage among the transistors TR _P and TR _N in the CMOS inverter IN ₃ of An output terminal t _O is derived from the connection point.

Further, CMOS inverters IN _{1 to} IN ₃
P source channel MOS field-effect transistor TR _P is connected to the positive DC power source VD, N-channel MOS field-effect transistor TR _N source current control circuit IC for the
N-channel MOS field effect transistor TC
₁ to Tc is ₃ through the ground, each N-channel MOS field-effect transistor TC ₁ to Tc of the current control circuit IC
_{The three} gates are connected to each other and to a control voltage source VC.

Then, each of the Ns constituting the current control circuit IC
By changing the control voltage V _C applied to each gate of the channel MOS field effect transistors TC _{1 to} TC ₃ , these N channel MOS field effect transistors TC
The on-resistance of ₁ to Tc ₃ is changed, the next stage of the gate of the CMOS inverter IN ₁ to IN ₃ - by charging and discharging current is changed to the source capacitance, variable control of the oscillation frequency of the voltage controlled oscillator can do.

[0006]

However, in the above-mentioned conventional voltage controlled oscillator, three MOS field effect transistors are connected in series between the DC power supply VD and the ground for one inverter. Will be. Therefore, the voltage to be supplied to one inverter increases, which hinders a reduction in voltage. Because of this,
This hinders a reduction in the voltage of the entire voltage-controlled oscillation circuit, and an improvement has been desired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional unsolved problem, and has as its object to provide a voltage-controlled oscillation circuit capable of reducing the voltage.

[0008]

According to a first aspect of the present invention, there is provided a voltage controlled oscillation circuit connected to an odd number of ring-connected inverters and an output line of the inverter. And current control means for controlling the current flowing through the inverter.

According to the first aspect of the present invention, current control means is connected to the output lines of the odd number of ring-connected inverters, and the current flowing through the inverter is controlled by the current control means. The frequency changes.

At this time, since the current control means is connected to the output line of the inverter, it is possible to reduce the voltage as compared with a case where the current control means and the inverter are connected in series.

According to a second aspect of the present invention, each of the inverters comprises a CMOS inverter, and the current control means is connected to a connection point between drains of MOS transistors constituting the CMOS inverter. And a control voltage source for controlling a gate voltage of the transistor unit.

According to the second aspect of the present invention, since the inverter is a CMOS inverter and the current control means is formed of a MOS transistor, the power consumption of the entire voltage controlled oscillator can be suppressed.

According to a third aspect of the present invention, the MOS transistor forming the transistor section has a higher threshold voltage than the MOS transistor forming the inverter.

According to the third aspect of the invention, the MOS transistor forming the transistor section is configured to have a higher threshold voltage than the MOS transistor forming the inverter. That is, the sensitivity to the current flowing through the inverter is M
M which constitutes the transistor unit rather than the OS transistor
The OS transistor is set to be slower. Therefore,
For example, even if the transistor unit is connected between the output line of the inverter and the ground side of the power supply voltage, the MOS transistor of the transistor unit is not sensitive to the current flowing through the inverter, so that the transistor unit does not short-circuit to the ground potential. .

According to a fourth aspect of the present invention, in the voltage-controlled oscillation circuit, the transistor unit includes a plurality of cascaded MOS transistors.

In the invention according to claim 4, the transistor section is constituted by a plurality of cascaded MOS transistors. Therefore, one MOS
Since the voltage between the source and the drain of the transistor becomes lower, it is difficult for the MOS transistor to be turned on, that is, a transistor with low sensitivity can be obtained.

Further, in the voltage controlled oscillation circuit according to the fifth aspect, a MOS transistor for frequency adjustment connected in series with a MOS transistor constituting the transistor unit, and a voltage applied to a gate of the MOS transistor for frequency adjustment And a frequency adjusting means for adjusting the frequency.

According to the fifth aspect of the present invention, the transistor section includes a frequency adjusting MOS transistor connected in series with the MOS transistor constituting the transistor section. Is adjusted by the frequency adjusting means.

Therefore, by changing the voltage applied to the gate of the frequency adjusting MOS transistor by the frequency adjusting means, the current flowing through the inverter is also controlled. For example, the oscillation frequency is determined by the current controlling means. If the fine adjustment of the actual oscillation frequency is performed by the frequency adjustment means, it is possible to obtain a highly accurate oscillation frequency.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an inverter unit that forms a ring oscillator by connecting an odd number of inverters in a ring, and 2 denotes a current control unit (current control unit) that controls a current flowing through the inverter unit 1. ,
It is connected between the output line of the inverter unit 1 and the ground.

Here, the inverter unit 1 has an odd number, for example,
Three CMOS inverters IN₁ ~ IN_Three Has a ring connection
And each CMOS inverter IN₁ ~
IN _Three Are P-channel MOS field-effect transistors.
Jista TR_P And N-channel MOS field effect transistor
TR_N Are connected in series by connecting both drains.
CMOS inverter IN₁ ~ IN_Three 
P-channel MOS field effect transistor TR_P 
Is the positive side of the DC power supply VD whose negative side is grounded.
And an N-channel MOS field effect transistor T
R_N Source is grounded.

Then, the first-stage CMOS inverter I
Connection point between the drains of the transistors TR _P and TR _N of N ₁ is connected to the gates of the transistors TR _P and TR _N of the CMOS inverter IN ₂ of the second stage, the 2
The connection point between the drains of both transistors TR _P and TR _N in the CMOS inverter IN ₂ of the third stage is connected to the gates of both transistors TR _P and TR _N of the CMOS inverter IN ₃ in the third stage. Transistors TR _P and TR _N in CMOS inverter IN ₃ of FIG.
Is connected to the gates of both transistors TR _P and TR _N of the first-stage CMOS inverter IN ₁ , thereby forming a ring connection.
An output terminal t _O is derived from a connection point between the drains of the transistors TR _P and TR _N in the OS inverter IN ₃ .

The current control unit 2 has three N-channels whose drains are connected to the connection points between the drains of the transistors TR _P and TR _N in each of the CMOS inverters IN _{1 to} IN ₃ of the inverter unit 1 and whose sources are grounded. MOS
Control transistor TC composed of a field effect transistor
_{1 to} TC ₃ (transistor unit), and the gates of these transistors TC _{1 to} TC ₃ are connected to each other and connected to the positive electrode of a control voltage source VC whose negative electrode is grounded.

Each of the control transistors TC _{1 to} TC ₃ in the current control section 2 has its threshold voltage V
_TH is set so as to be larger than the threshold voltage V _TH of each MOS field-effect transistor constituting the inverter unit 1, that is, the sensitivity to the inverter current If flowing through the inverters IN _{1 to} IN ₃ becomes lower. It is set as follows.

The threshold voltage V _TH can be set by selecting the gate length and gate width of each of the control transistors TC _{1 to} TC _3. The gate length can be increased or the gate width can be reduced. By doing so, the threshold voltage V _TH increases.

The threshold voltage V _TH may be set according to the variable width of the frequency.
₁ to Tc ₃ is because it is a transistor for frequency control, designed so as not to widen the variable range of frequency than necessary. If it is desired to increase the change width of the frequency, the threshold voltage V _TH is set to a relatively small value so as to operate as an ideal switch. Since the change width of the control current Id is large, that is, the change width of the frequency can be increased. Conversely, if the threshold voltage V _TH is increased,
Since the change width of the control current Id is smaller than the change width of the gate voltage, the change width of the frequency can be reduced.

Next, the operation of the first embodiment will be described.

In the inverter section 1, when a signal input to the gate of each of the CMOS inverters IN _{1 to} IN ₃ changes from a high level to a low level (or from a low level to a high level), the next stage responds accordingly. The capacitance is charged (or discharged). Then, it is determined by the charge current amount (or discharge current amount) at this time, that is, the inverter current If.

Here, the inverter current If is closely related to the frequency of the oscillation output and the inverter current If
Is equivalent to changing the oscillation frequency, and the inverter current If is a basic parameter that determines the oscillation frequency. That is, by changing the control current Id, the inverter current If changes, that is, the oscillation frequency can be changed.

In this state, when a voltage is applied to the gates of the control transistors TC _{1 to} TC ₃ of the current control unit 2,
Since the control current Id flows according to the applied voltage, as a result, increases the current flowing through the transistor TR _P is, the oscillation frequency will vary in accordance with the control current Id. That is, it is possible to change the oscillation frequency by changing the voltage applied to the control transistor TC ₁ ~TC _3.

At this time, the control transistors TC _{1 to} TC ₁
The threshold voltage V _TH of C ₃ is determined by each CMOS inverter IN
The threshold voltages V _TH of the MOS field-effect transistors constituting the transistors _{1 to} IN ₃ are set to be higher than the threshold voltages V _TH , and the sensitivity to the inverter current If is reduced by the CMOS inverters IN _{1 to} IN ₃
, The control transistors TC _{1 to} TC ₃ are not turned on, and each CMOS inverter IN
The outputs of _{1 to} IN ₃ are not short-circuited to the ground potential.

Here, the control transistors TC _{1 to} TC
₃ is interposed between the output lines of the CMOS inverters IN _{1 to} IN ₃ and the ground, and connected in series between the DC power supply VD and the ground to form the CMOS inverters IN _{1 to} IN ₃ . Only two transistors will be interposed.

Therefore, while three MOS field-effect transistors are conventionally connected in series between DC power supply VD and ground as shown in FIG. 5, according to the above embodiment, DC power supply VD and ground Since only two transistors constituting the CMOS inverters IN _{1 to} IN ₃ are interposed between the DC power supply VD and the ground, the number of transistors interposed between the DC power supply VD and the ground is reduced, so that the voltage can be reduced. .

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The second embodiment is the same as the circuit diagram of the first embodiment shown in FIG. 1 except that the configuration of the current control unit 2 is different, so that detailed description of the same unit is omitted. I do.

The current control unit 2 according to the second embodiment is different from the current control unit 2 shown in FIG. 1 in that the control transistors TC _{1 to} TC ₃ are connected to the control transistors TC _{1 to} TC _3.
Control transistor TC ₁₁ consisting of N-channel MOS field-effect transistor having the same characteristics as ₁ to Tc ₃ through T
The C ₁₃ are connected in cascade. That is, the transistors TC ₁₁ to Tc for controlling the source of the _thirteenth transistor TC ₁
Connected to the source of to Tc _3, grounding the drain, further to its gate, is connected to the positive electrode side of the control voltage source VC.

[0037] Therefore, similar to the form in this case is also the first embodiment, by applying a control voltage V _C to the gate of the control transistor TC ₁ to Tc ₃ and TC ₁₁ to Tc _13, the control current Id Flows, and as a result, the inverter current If changes, so that the oscillation frequency can be changed according to the control voltage V _C.

Here, as shown in the first embodiment,
And a control transistor TC₁ ~ TC_Three The inverter
It is difficult to design so that the sensitivity to the current If becomes low.
It is difficult. However, in the second embodiment, the control
Transistor TC₁ ~ TC _Three And TC₁₁~ TC₁₃Directly
Connected to the row, so that the source
The inter-rain voltage is smaller and the control transistor
Is less sensitive. Therefore, doing this
And the control transistor TC having low sensitivity.₁ ~ T
C_Three Can be easily obtained.

In the second embodiment,
Control transistor TC ₁ to Tc ₃ and TC ₁₁ to Tc ₁₃
Are described in series, but the present invention is not limited to this, and three or more control transistors may be connected.

The control transistors TC _{1 to} TC ₃
Has been described using the TC ₁₁ to Tc ₁₃ having the same characteristics as, not limited to this, it is also possible to apply having different characteristics.

Next, a third embodiment of the present invention will be described.

The voltage control type according to the third embodiment
The oscillation circuit is, as shown in FIG. 3, a voltage control type shown in FIG.
In the oscillation circuit, a control transistor of the current control unit 2
TC ₁ ~ TC_Three N-channel MOS field effect between ground and ground
Transistor with oscillation transistor for adjusting oscillation frequency
TA TC_{twenty one}~ TC_{twenty three}(Frequency adjustment MOS transistor)
Are connected in series. That is, the control transistor T
C₁ ~ TC_Three Oscillation frequency adjustment transistor at the source
TC_{twenty one}~ TC_{twenty three}Connect the drain of
Transistor TC_{twenty one}~ TC_{twenty three}Ground the source of the
DA converter (DAC) (frequency adjustment means) 1
Oscillation frequency adjustment voltage V which is an output of 0 _F I will apply
Swelling.

The oscillation frequency adjusting transistor TC ₂₁
The to Tc _23, for example, the control transistor T
A transistor having a current supply amount equal to or larger than the current supply amounts of C _{1 to} TC ₃ is used. Then, the oscillation by reducing the drain current flowing through the oscillation frequency adjustment transistor TC ₂₁ to Tc ₂₃ by the frequency adjusting the adjustment voltage V _F, decreases the control current Id, changing the inverter current If This changes the oscillation frequency.

Therefore, the oscillation frequency can be adjusted by adjusting the control current Id by the control voltage V _C , and the oscillation frequency can be adjusted by adjusting the oscillation frequency adjustment voltage V _F output from the DA converter 10. The current Id can be adjusted, that is, the oscillation frequency can be adjusted.

Thus, for example, if the DA converter 10 is operated so that the oscillation frequency at a certain control voltage V _C becomes a predetermined frequency and the output of the DA converter 10 is fixed, the output of each MOS field-effect transistor It is possible to adjust the deviation of the oscillation frequency due to the variation in the characteristics and the like, and it is possible to obtain a more accurate voltage-controlled oscillation circuit.

When the oscillation stops for some reason or the oscillation frequency fluctuates, the oscillation frequency can be finely adjusted by operating the DA converter 10 and adjusting the control current Id. it can.

The adjustment by the DA converter 10 may be performed before shipment, or the user may make fine adjustments as needed.

In each of the above embodiments, the threshold voltage V _TH of the control transistors TC _{1 to} TC ₃ is
The case where the threshold voltage V _TH of each MOS field effect transistor constituting the inverter unit 1 is set to be higher than the threshold voltage V _TH has been described. However, the present invention is not necessarily limited to this, and the point is that the control transistors TC _{1 to} TC ₃ is turned on and the output of each of the CMOS inverters IN _{1 to} IN ₃ can be prevented from being short-circuited to the ground, and can be set according to the control voltage Vc.

Further, in each of the above embodiments, the case where the N-channel MOS field-effect transistor is used as the field-effect transistor constituting the current control unit 2 has been described. However, the present invention is not limited to this.
An OS field-effect transistor can also be used.

In this case, for example, as shown in FIG.
Instead of the N-channel field-effect transistor TC ₁ to Tc ₃ in the voltage controlled oscillation circuit shown in, using a P-channel field effect transistor TC _P1 to Tc _P3, its source connected to the positive electrode side of the DC power source VD, the drain Each CMOS
It is connected to a connection point between the drains of both transistors of the inverters IN _{1 to} IN ₃ . Further, the transistors TC _{P1 to} T _{P1 to} T
The gate of the C _P3, applying a control voltage V _C.

By adjusting the control voltage V _C , the control current I flowing through the transistors TC _{P1 to} TC _P3 is controlled.
d changes, and this is changed by each of the CMOS inverters IN _{1 to} IN _1.
Since it is added to the inverter current If flowing through ₃ , the oscillation frequency changes as a result of a change in the inverter current If.

Therefore, even when the current control section 2 is constituted by the P-channel field-effect transistors TC _{P1 to} TC _P3 , the same operation and effect as those of the first embodiment can be obtained. . Further, in each of the above-described embodiments, the case where the inverter unit 1 is ring-connected to three CMOS inverters is described. However, the present invention is not limited to this, and five or more odd-numbered CMOS inverters may be ring-connected. It may be. In each of the above embodiments, the inverter unit 1 and the current control unit 2
Has been described in the case where the current control element is constituted by a MOS field effect transistor. However, the present invention is not limited to this, and another current control element such as a junction field effect transistor or a bipolar transistor can be applied. it can.

Further, in each of the above embodiments, the control transistors are replaced by CMOS inverters IN _{1 to} IN _3.
Has been described, but the present invention is not limited to this. It is desirable to provide each of the CMOS inverters. However, for example, it may be provided to only one or some of the CMOS inverters.
If not provided for all CMOS inverters,
It is desirable to provide at least the output stage.

[0054]

As described above, according to the first aspect of the present invention,
In the voltage-controlled oscillation circuit according to the above, the current control means for controlling the current flowing through the inverter is connected to the output line of the inverter, so that the voltage of the entire voltage-controlled oscillation circuit can be reduced. Further, in the voltage controlled oscillation circuit according to the second aspect, since the inverter is a CMOS inverter and the current control means is formed of a MOS transistor, the power consumption of the entire voltage controlled oscillation circuit can be suppressed. According to a third aspect of the present invention, the MOS transistor forming the transistor section has a threshold voltage higher than that of the MOS transistor forming the inverter, and the sensitivity to the current flowing through the inverter forms the inverter. Since the MOS transistors constituting the transistor section are made duller than the MOS transistors to be formed, the transistor section does not short-circuit. Further, in the voltage-controlled oscillation circuit according to the fourth aspect, since the transistor section is constituted by a plurality of MOS transistors connected in cascade, a transistor having low sensitivity can be easily obtained.

Further, the voltage controlled oscillation circuit according to claim 5 is provided with a frequency adjusting MOS transistor so as to control the current flowing through the inverter by adjusting the voltage applied to the gate by the frequency adjusting means. Therefore, a more accurate oscillation frequency can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a voltage-controlled oscillation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a voltage-controlled oscillation circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a voltage-controlled oscillation circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of another voltage-controlled oscillation circuit according to the present invention.

FIG. 5 is a circuit diagram showing a conventional voltage controlled oscillation circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 Inverter section IN _{1 to} IN ₃ CMOS inverter TR _P P-channel MOS field-effect transistor TR _N N-channel MOS field-effect transistor VD DC voltage source 2 Current control section TC _{1 to} TC ₃ Control transistor TC _{11 to} TC ₁₃ N-channel MOS Field effect transistors TC _{21 to} TC ₂₃ Oscillation frequency adjusting transistors TC _{P1 to} TC _P3 P-channel MOS field effect transistors VC Control voltage source 10 DA converter

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yo Yamaguchi 1-2-1 Uchisaiwai-cho, Chiyoda-ku, Tokyo Sogo Communication Engineering Co., Ltd. F-term (reference) 5J043 AA03 AA22 LL01

Claims (5)

[Claims] 1. A voltage controlled oscillator circuit comprising: an odd number of ring-connected inverters; and current control means connected to an output line of the inverter and controlling a current flowing through the inverter. 2. The method according to claim 1, wherein each of the inverters comprises a CMOS inverter, and wherein the current control means comprises a transistor unit comprising a MOS transistor connected to a connection point between drains of MOS transistors constituting the CMOS inverter;
2. The voltage controlled oscillation circuit according to claim 1, further comprising a control voltage source for controlling a gate voltage of the transistor unit. 3. The voltage controlled oscillation circuit according to claim 2, wherein the MOS transistor forming the transistor section has a higher threshold voltage than the MOS transistor forming the inverter. 4. The voltage controlled oscillation circuit according to claim 2, wherein said transistor section is constituted by a plurality of cascaded MOS transistors. 5. A frequency adjusting MOS transistor connected in series with a MOS transistor constituting the transistor section, and frequency adjusting means for adjusting a voltage applied to a gate of the frequency adjusting MOS transistor. 5. The voltage controlled oscillation circuit according to claim 2, wherein