JP2010093761A5

JP2010093761A5 -

Info

Publication number: JP2010093761A5
Application number: JP2008264634A
Authority: JP
Filing date: 2008-10-10
Publication date: 2011-11-10
Anticipated expiration: 2028-10-10

Claims

An oscillation unit that generates an internal signal by oscillating at a frequency according to the input voltage, a frequency dividing unit that divides the internal signal to generate a divided signal, and a reference signal input from the outside A PLL circuit having a phase comparison unit that compares a phase with the phase of the frequency-divided signal and outputs a phase error signal according to a comparison result, and a generation unit that generates a control voltage based on the phase error signal. There,
A switching unit that switches between a first state in which the control voltage is input to the oscillation unit and a second state in which a reference voltage is input to the oscillation unit;
In the second state, the control voltage is compared with the reference voltage, and the oscillation frequency in the oscillation unit is corrected with respect to the voltage input to the oscillation unit so that the control voltage becomes equal to the reference voltage. And a correction unit that
The correction unit corrects a gain of the oscillation unit that is a characteristic of an oscillation frequency in the oscillation unit with respect to a voltage input to the oscillation unit, so that the control voltage becomes equal to the reference voltage,
The oscillation unit is
An input transistor to which the control voltage or the reference voltage is input to a gate;
A current mirror circuit for passing a current according to a current flowing between the source and drain of the input transistor;
A ring oscillator that receives a current passed by the current mirror circuit and oscillates at a frequency according to the magnitude of the received current,
The correction unit includes a MOS transistor whose mutual conductance is controlled based on a comparison result between the control voltage and the reference voltage,
When the control voltage is higher than the reference voltage, the transconductance of the MOS transistor decreases, and when the control voltage is lower than the reference voltage, the transconductance of the MOS transistor increases.
The correction unit is
Comparing the reference voltage with the previous SL control voltage, a voltage comparison unit for outputting a voltage error signal corresponding to the comparison result,
A holding unit that temporarily holds the previous SL voltage error signal,
A control value holding unit that changes the held digital control value according to the voltage error signal temporarily held in the holding unit and output from the holding unit, and holds the changed digital control value; ,
A D / A converter that generates an analog control value by D / A converting the changed digital control value held in the control value holding unit and output from the control value holding unit;
The analog control value is input to a gate, a source connected to a ground voltage, a drain PLL circuit you comprising the, said MOS transistor connected to the source of the input transistor.

When the voltage error signal indicates that the control voltage is higher than the reference voltage, the control value holding unit counts up the held digital control value and outputs the counted up digital control value. If the voltage error signal indicates that the control voltage is lower than the reference voltage, count down the held digital control value, hold the counted down digital control value,
When the analog control value corresponding to the counted-up digital control value is input to the gate, the MOS transistor increases the magnitude of the current flowing between the source and the drain of the input transistor, and the counted-down digital control value When an analog control value corresponding to the control value is input to the gate, the magnitude of the current flowing between the source and drain of the input transistor is reduced,
The gain of the oscillating unit increases as the current flowing between the source and drain of the input transistor increases, and decreases as the current flowing between the source and drain of the input transistor decreases. The PLL circuit according to claim 1 .

The correction unit is
A differential amplifier for generating and outputting a differential signal of the previous SL control voltage and the reference voltage,
A holding unit for temporarily holding the differential voltage corresponding to the prior SL differential signal,
An A / D converter that A / D converts the differential voltage held by the holding unit to generate a digital control value;
A D / A converter that generates an analog control value by D / A converting the digital control value;
Is input before Symbol analog control value to the gate, a source connected to a ground voltage, a drain PLL circuit according to claim 1, characterized in that it comprises, said MOS transistor connected to the source of the input transistor .

When the differential amplification unit outputs the differential signal indicating that the control voltage is higher than the reference voltage, the differential amplification unit increases the differential voltage held by the holding unit and increases the differential voltage. Is held by the holding unit, and the differential signal indicating that the control voltage is lower than the reference voltage is output, the differential voltage held by the holding unit is decreased, and the reduced differential Holding the voltage in the holding unit,
When the analog control value corresponding to the increased differential voltage is input to the gate, the MOS transistor increases the amount of current flowing between the source and the drain of the input transistor, and reduces the decreased differential. When an analog control value corresponding to the voltage is input to the gate, the magnitude of the current flowing between the source and drain of the input transistor is reduced,
The gain of the oscillating unit increases as the current flowing between the source and drain of the input transistor increases, and decreases as the current flowing between the source and drain of the input transistor decreases. The PLL circuit according to claim 3 .

The generator is
A charge pump circuit including a capacitor and generating a charge pump current by charging or discharging the capacitor based on the phase error signal;
A low-pass filter that generates the control voltage by smoothing the charge pump current output from the charge pump circuit;
PLL circuit according to claim 1, any one of 4, which comprises a.

The switching unit is
A first control switch for switching conduction between the generation unit and the oscillation unit;
A second control switch for switching conduction between the reference voltage and the oscillation unit;
Including
In the first state, the first control switch is turned on and the second control switch is turned off.
The PLL according to any one of claims 1 to 5 , wherein, in the second state, the first control switch is turned off and the second control switch is turned on. circuit.

PLL circuit according to any one of claims 1 6, characterized in that the said second state upon activation of the PLL circuit.