JP2010093762A5 - - Google Patents
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- JP2010093762A5 JP2010093762A5 JP2008264635A JP2008264635A JP2010093762A5 JP 2010093762 A5 JP2010093762 A5 JP 2010093762A5 JP 2008264635 A JP2008264635 A JP 2008264635A JP 2008264635 A JP2008264635 A JP 2008264635A JP 2010093762 A5 JP2010093762 A5 JP 2010093762A5
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Claims (11)
前記制御電圧が前記発振部へ入力される第１の状態と、参照電圧が前記発振部へ入力される第２の状態とを切り替える切り替え部と、
前記第２の状態において、前記分周信号の周波数と前記基準信号の周波数とを比較し、前記分周信号の周波数が前記基準信号の周波数に等しくなるように、前記発振部に入力された電圧に対する前記発振部における発振の周波数を補正する補正部と、を備え、
前記補正部は、前記分周信号の周波数が前記基準信号の周波数に等しくなるように、前記発振部に入力された電圧に対する前記発振部における発振の周波数の特性である前記発振部のゲインを補正し、
前記発振部は、
前記制御電圧または前記参照電圧がゲートに入力される入力トランジスタと、
前記入力トランジスタのソース−ドレイン間を流れる電流に応じた電流を流すカレントミラー回路と、
前記カレントミラー回路により流された電流を受けて、受けた電流の大きさに応じた周波数で発振するリングオシレータと、を含み、
前記補正部は、前記基準信号の周波数と前記分周信号の周波数との比較結果に基づいて相互コンダクタンスが制御されるＭＯＳトランジスタを含み、
前記分周信号の周波数が前記基準信号の周波数よりも高い場合、前記ＭＯＳトランジスタの相互コンダクタンスが減少し、
前記分周信号の周波数が前記基準信号の周波数よりも低い場合、前記ＭＯＳトランジスタの相互コンダクタンスが増大し、
前記補正部は、
前記分周信号の周波数と外部から受けた前記基準信号の周波数とを比較し、比較結果に応じた差信号を出力する周波数比較部と、
前記差信号に応じて、保持しているデジタル制御値を変更して、変更されたデジタル制御値を保持する制御値保持部と、
前記制御値保持部に保持され前記制御値保持部から出力された前記変更されたデジタル制御値をＤ／Ａ変換することにより、アナログ制御値を生成するＤ／Ａ変換部と、
前記アナログ制御値がゲートに入力され、ソースが基準電圧に接続され、ドレインが前記入力トランジスタのソースに接続された前記ＭＯＳトランジスタと、を含む
ことを特徴とするＰＬＬ回路。 An oscillation unit that generates an internal signal by oscillating at a frequency according to the input voltage, a frequency dividing unit that divides the internal signal to generate a divided signal, and a reference signal input from the outside A PLL circuit having a phase comparison unit that compares a phase with the phase of the frequency-divided signal and outputs a phase error signal according to a comparison result, and a generation unit that generates a control voltage based on the phase error signal. There,
A switching unit that switches between a first state in which the control voltage is input to the oscillation unit and a second state in which a reference voltage is input to the oscillation unit;
In the second state, the frequency of the divided signal is compared with the frequency of the reference signal, and the voltage input to the oscillation unit so that the frequency of the divided signal is equal to the frequency of the reference signal A correction unit for correcting the frequency of oscillation in the oscillation unit with respect to
The correction unit corrects the gain of the oscillation unit, which is a characteristic of the oscillation frequency in the oscillation unit with respect to the voltage input to the oscillation unit, so that the frequency of the divided signal is equal to the frequency of the reference signal. And
The oscillation unit is
An input transistor to which the control voltage or the reference voltage is input to a gate;
A current mirror circuit for passing a current according to a current flowing between the source and drain of the input transistor;
A ring oscillator that receives a current passed by the current mirror circuit and oscillates at a frequency according to the magnitude of the received current,
The correction unit includes a MOS transistor whose mutual conductance is controlled based on a comparison result between the frequency of the reference signal and the frequency of the divided signal,
When the frequency of the divided signal is higher than the frequency of the reference signal, the transconductance of the MOS transistor is reduced,
When the frequency of the divided signal is lower than the frequency of the reference signal, the transconductance of the MOS transistor increases,
The correction unit is
A frequency comparing unit which compares the frequency of the reference signal received from the frequency and the outside of the front Symbol divided signal, and outputs a difference signal corresponding to the comparison result,
Depending on the prior SL-difference signals, by changing the digital control value held, the control value holding unit for holding the modified digital control value,
A D / A converter that generates an analog control value by D / A converting the changed digital control value held in the control value holding unit and output from the control value holding unit;
Before Symbol analog control value is input to a gate, a source connected to a reference voltage, a drain PLL circuit you comprising the, said MOS transistor connected to the source of the input transistor.
前記分周部から受けた前記分周信号のクロック数をカウントすることにより、前記分周信号の周波数を計る第１のカウンタと、
外部から受けた前記基準信号のクロック数をカウントすることにより、前記基準信号の周波数を計る第２のカウンタと、
前記第２のカウンタのカウント値から前記第１のカウンタのカウント値を減算することにより、前記差信号を生成して出力する減算器と、
を含む
ことを特徴とする請求項１に記載のＰＬＬ回路。 The frequency comparison unit
A first counter that measures the frequency of the divided signal by counting the number of clocks of the divided signal received from the dividing unit;
A second counter for measuring the frequency of the reference signal by counting the number of clocks of the reference signal received from the outside;
A subtractor that generates and outputs the difference signal by subtracting the count value of the first counter from the count value of the second counter;
The PLL circuit according to claim 1 , comprising:
前記ＭＯＳトランジスタは、前記カウントアップされたデジタル制御値に対応したアナログ制御値がゲートに入力された場合、前記入力トランジスタのソース−ドレイン間に流れる電流の大きさを増加させ、前記カウントダウンされたデジタル制御値に対応したアナログ制御値がゲートに入力された場合、前記入力トランジスタのソース−ドレイン間に流れる電流の大きさを減少させ、
前記発振部のゲインは、前記入力トランジスタのソース−ドレイン間に流れる電流の大きさが増加することにより上がり、前記入力トランジスタのソース−ドレイン間に流れる電流の大きさが減少することにより下がる
ことを特徴とする請求項１に記載のＰＬＬ回路。 When the difference signal indicates that the frequency of the divided signal is lower than the frequency of the reference signal, the control value holding unit counts up the held digital control value and is counted up When the difference signal indicates that the frequency of the frequency-divided signal is higher than the frequency of the reference signal, the digital control value is held down, and the held-down digital control value is counted down. Hold the value,
When the analog control value corresponding to the counted-up digital control value is input to the gate, the MOS transistor increases the magnitude of the current flowing between the source and drain of the input transistor, and the counted-down digital control value When an analog control value corresponding to the control value is input to the gate, the magnitude of the current flowing between the source and drain of the input transistor is reduced,
The gain of the oscillating unit increases as the current flowing between the source and drain of the input transistor increases, and decreases as the current flowing between the source and drain of the input transistor decreases. The PLL circuit according to claim 1 .
前記制御電圧が前記発振部へ入力される第１の状態と、第１の参照電圧が前記発振部へ入力される第３の状態と、前記第１の参照電圧より高い第２の参照電圧が前記発振部へ入力される第４の状態とを切り替える切り替え部と、
前記第３の状態における前記分周信号の周波数と前記第４の状態における前記分周信号の周波数との周波数差の絶対値と目標値とを比較し、前記第３の状態における前記分周信号の周波数と前記第４の状態における前記分周信号の周波数との周波数差の絶対値が目標値に等しくなるように、前記発振部に入力された電圧に対する前記発振部における発振の周波数を補正する補正部と、
を備えたことを特徴とするＰＬＬ回路。 An oscillation unit that generates an internal signal by oscillating at a frequency according to the input voltage, a frequency dividing unit that divides the internal signal to generate a divided signal, and a reference signal input from the outside PLL circuit having a phase comparator which compares the phase and prior SL-divided signal phase, and outputs a phase error signal corresponding to the comparison result, and a generating unit for generating a control voltage based on the phase error signal Because
A first state in which pre-SL control voltage is input to the oscillation portion, the third state and the higher than first reference voltage second reference voltage first reference voltage is input to said oscillating unit A switching unit that switches between a fourth state input to the oscillation unit;
The absolute value of the frequency difference between the frequency of the frequency-divided signal in the third state and the frequency of the frequency-divided signal in the fourth state is compared with a target value, and the frequency-divided signal in the third state the absolute value of the frequency difference to be equal to the target value, corrects the frequency of oscillation of the oscillation portion with respect to the voltage input to the oscillating unit of the frequency and the frequency of the divided signal in said fourth state A correction unit;
A PLL circuit comprising:
ことを特徴とする請求項４に記載のＰＬＬ回路。 The correction unit is configured so that the absolute value of the frequency difference between the frequency of the divided signal in the third state and the frequency of the divided signal in the fourth state is equal to a target value. PLL circuit according to claim 4, characterized in that to correct the gain of the oscillating unit which is characteristic of the frequency of oscillation of the oscillation portion with respect to the input voltage.
ことを特徴とする請求項５に記載のＰＬＬ回路。 The correction unit reduces the gain of the oscillation unit when the absolute value of the frequency difference is greater than the target value so that the gain of the oscillation unit increases when the absolute value of the frequency difference is less than the target value. The PLL circuit according to claim 5 , wherein the gain of the oscillating unit is corrected.
前記制御電圧または参照電圧がゲートに入力される入力トランジスタと、
前記入力トランジスタのソース−ドレイン間を流れる電流に応じた電流を流すカレントミラー回路と、
前記カレントミラー回路により流された電流を受けて、受けた電流の大きさに応じた周波数で発振するリングオシレータと、を含む
ことを特徴とする請求項５または６に記載のＰＬＬ回路。 The oscillation unit is
An input transistor to which the control voltage or reference voltage is input to the gate;
A current mirror circuit for passing a current according to a current flowing between the source and drain of the input transistor;
The PLL circuit according to claim 5 , further comprising: a ring oscillator that receives a current passed by the current mirror circuit and oscillates at a frequency corresponding to a magnitude of the received current.
前記分周信号の周波数が前記基準信号の周波数よりも高い場合、前記ＭＯＳトランジスタの相互コンダクタンスが減少し、
前記分周信号の周波数が前記基準信号の周波数よりも低い場合、前記ＭＯＳトランジスタの相互コンダクタンスが増大する
ことを特徴とする請求項７に記載のＰＬＬ回路。 The correction unit includes a MOS transistor whose mutual conductance is controlled based on a comparison result between the frequency of the reference signal and the frequency of the divided signal,
When the frequency of the divided signal is higher than the frequency of the reference signal, the transconductance of the MOS transistor is reduced,
8. The PLL circuit according to claim 7 , wherein the transconductance of the MOS transistor increases when the frequency of the divided signal is lower than the frequency of the reference signal.
前記周波数差の絶対値と前記目標値とを比較し、比較結果に応じた差信号を出力する周波数差比較部と、
前記差信号に応じて、保持しているデジタル制御値を変更して、変更されたデジタル制御値を保持する制御値保持部と、
前記制御値保持部に保持され前記制御値保持部から出力された前記変更されたデジタル制御値をＤ／Ａ変換することにより、アナログ制御値を生成するＤ／Ａ変換部と、
前記アナログ制御値がゲートに入力され、ソースが基準電圧に接続され、ドレインが前記入力トランジスタのソースに接続された前記ＭＯＳトランジスタと、を含む
ことを特徴とする請求項８に記載のＰＬＬ回路。 The correction unit is
A frequency difference comparison unit that compares the absolute value of the frequency difference with the target value and outputs a difference signal according to the comparison result;
Depending on the prior SL-difference signals, by changing the digital control value held, the control value holding unit for holding the modified digital control value,
A D / A converter that generates an analog control value by D / A converting the changed digital control value held in the control value holding unit and output from the control value holding unit;
Is input before Symbol analog control value to the gate, a source connected to a reference voltage, a drain PLL circuit according to claim 8, characterized in that it comprises, said MOS transistor connected to the source of the input transistor .
前記第３の状態における前記分周信号のクロック数をカウントすることにより、前記第３の状態における前記分周信号の周波数を計る第３のカウンタと、
前記第４の状態における前記分周信号のクロック数をカウントすることにより、前記第４の状態における前記分周信号の周波数を計る第４のカウンタと、
前記第４のカウンタのカウント値から前記第３のカウンタのカウント値を減算するとともに減算した結果から前記目標値をさらに減算することにより、前記差信号を生成して出力する減算器と、を含む
ことを特徴とする請求項９に記載のＰＬＬ回路。 The frequency difference comparison unit includes:
A third counter for measuring the frequency of the divided signal in the third state by counting the number of clocks of the divided signal in the third state;
A fourth counter for measuring the frequency of the divided signal in the fourth state by counting the number of clocks of the divided signal in the fourth state;
A subtractor that subtracts the count value of the third counter from the count value of the fourth counter and generates and outputs the difference signal by further subtracting the target value from the subtraction result. The PLL circuit according to claim 9 .
前記ＭＯＳトランジスタは、前記カウントアップされたデジタル制御値に対応したアナログ制御値がゲートに入力された場合、前記入力トランジスタのソース−ドレイン間に流れる電流の大きさを増加させ、前記カウントダウンされたデジタル制御値に対応したアナログ制御値がゲートに入力された場合、前記入力トランジスタのソース−ドレイン間に流れる電流の大きさを減少させ、
前記発振部のゲインは、前記入力トランジスタのソース−ドレイン間に流れる電流の大きさが増加することにより上がり、前記入力トランジスタのソース−ドレイン間に流れる電流の大きさが減少することにより下がる
ことを特徴とする請求項９に記載のＰＬＬ回路。 The control value holding unit counts up the held digital control value when the difference signal indicates that the absolute value of the frequency difference is less than the target value, and the counted-up digital control If the difference signal indicates that the absolute value of the frequency difference is greater than the target value, the held digital control value is counted down and the counted down digital control value is held. ,
When the analog control value corresponding to the counted-up digital control value is input to the gate, the MOS transistor increases the magnitude of the current flowing between the source and the drain of the input transistor, and the counted-down digital control value When an analog control value corresponding to the control value is input to the gate, the magnitude of the current flowing between the source and drain of the input transistor is reduced,
The gain of the oscillating unit increases as the current flowing between the source and drain of the input transistor increases, and decreases as the current flowing between the source and drain of the input transistor decreases. The PLL circuit according to claim 9 .
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008264635A JP5264401B2 (en) | 2008-10-10 | 2008-10-10 | PLL circuit |
| US12/560,395 US8085098B2 (en) | 2008-10-10 | 2009-09-15 | PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008264635A JP5264401B2 (en) | 2008-10-10 | 2008-10-10 | PLL circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010093762A JP2010093762A (en) | 2010-04-22 |
| JP2010093762A5 true JP2010093762A5 (en) | 2011-11-10 |
| JP5264401B2 JP5264401B2 (en) | 2013-08-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008264635A Expired - Fee Related JP5264401B2 (en) | 2008-10-10 | 2008-10-10 | PLL circuit |
Country Status (1)
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| JP (1) | JP5264401B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59132214A (en) * | 1983-01-19 | 1984-07-30 | Toshiba Corp | Gain variable circuit |
| US5999028A (en) * | 1997-12-22 | 1999-12-07 | Hewlett-Packard Company | Differential circuits with adjustable propagation timing |
| JP3425426B2 (en) * | 2000-01-31 | 2003-07-14 | 松下電器産業株式会社 | Transconductor and filter circuits |
| JP4273729B2 (en) * | 2002-09-18 | 2009-06-03 | ソニー株式会社 | Variable gain amplifier |
| JP4866707B2 (en) * | 2006-11-10 | 2012-02-01 | パナソニック株式会社 | PLL circuit and signal transmission / reception system |
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2008
- 2008-10-10 JP JP2008264635A patent/JP5264401B2/en not_active Expired - Fee Related
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