JP5203340B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5203340B2 JP5203340B2 JP2009273840A JP2009273840A JP5203340B2 JP 5203340 B2 JP5203340 B2 JP 5203340B2 JP 2009273840 A JP2009273840 A JP 2009273840A JP 2009273840 A JP2009273840 A JP 2009273840A JP 5203340 B2 JP5203340 B2 JP 5203340B2
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- etching
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 40
- 239000000758 substrate Substances 0.000 claims description 140
- 238000005530 etching Methods 0.000 claims description 139
- 238000000034 method Methods 0.000 claims description 108
- 229920002120 photoresistant polymer Polymers 0.000 claims description 85
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 4
- 238000009434 installation Methods 0.000 claims 2
- 239000010408 film Substances 0.000 description 81
- 238000012545 processing Methods 0.000 description 36
- 239000010409 thin film Substances 0.000 description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 229910052814 silicon oxide Inorganic materials 0.000 description 23
- 238000009623 Bosch process Methods 0.000 description 19
- 238000006116 polymerization reaction Methods 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 10
- 238000011900 installation process Methods 0.000 description 9
- 235000020637 scallop Nutrition 0.000 description 6
- 241000237503 Pectinidae Species 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000237509 Patinopecten sp. Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Description
(第1の実施の形態)
最初に、図1から図5を参照し、第1の実施の形態に係る半導体装置の製造方法について説明する。
(第2の実施の形態)
次に、図6及び図7を参照し、第2の実施の形態に係る半導体装置の製造方法について説明する。
(第3の実施の形態)
次に、図8及び図9を参照し、第3の実施の形態に係る半導体装置の製造方法について説明する。
(第4の実施の形態)
次に、図10及び図11を参照し、第4の実施の形態に係る半導体装置の製造方法について説明する。
9 下部電極(載置台)
101、S 基板(半導体ウェハ)
102、102a フォトレジスト膜
103、103a 開口部
104、105、105a 穴
106、106a 薄い膜
107、107a 深穴
Claims (4)
- シリコン基板上に開口部を有するフォトレジスト膜が形成された前記シリコン基板をエッチングチャンバ内に設置する設置工程と、
前記フォトレジスト膜をマスクとして、SiF4とO2とを含むガスを用いて、前記エッチングチャンバ内に設置された前記シリコン基板をエッチングする第1のエッチング工程と、
前記第1のエッチング工程に続いて、SF6とO2とHBrとを含むガスを用いて前記シリコン基板をエッチングし、前記シリコン基板に穴を形成する第2のエッチング工程と
を有し、
前記第1のエッチング工程の前に、予め前記開口部の開口幅寸法と略等しい深さまで前記シリコン基板をエッチングする予備エッチング工程を有する、半導体装置の製造方法。 - 前記第2のエッチング工程に続いて、フルオロカーボンを含むガスを用いて、前記シリコン基板をエッチングする第3のエッチング工程を有する、請求項1記載の半導体装置の製造方法。
- 前記設置工程において、前記シリコン基板を前記エッチングチャンバ内に設けられた載置台に載置し、
前記第3のエッチング工程において、前記載置台に載置された前記シリコン基板の自己バイアス電圧が50V以下の条件でエッチングする、請求項2に記載の半導体装置の製造方法。 - 前記第1のエッチング工程において、前記載置台に載置された前記シリコン基板の自己バイアス電圧が50V以下の条件でエッチングする、請求項3に記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009273840A JP5203340B2 (ja) | 2009-12-01 | 2009-12-01 | 半導体装置の製造方法 |
KR1020127013814A KR101295889B1 (ko) | 2009-12-01 | 2010-11-17 | 반도체 장치의 제조 방법 |
PCT/JP2010/070464 WO2011068029A1 (ja) | 2009-12-01 | 2010-11-17 | 半導体装置の製造方法 |
US13/512,372 US8716144B2 (en) | 2009-12-01 | 2010-11-17 | Method for manufacturing semiconductor device |
TW099141327A TWI445080B (zh) | 2009-12-01 | 2010-11-30 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009273840A JP5203340B2 (ja) | 2009-12-01 | 2009-12-01 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011119359A JP2011119359A (ja) | 2011-06-16 |
JP5203340B2 true JP5203340B2 (ja) | 2013-06-05 |
Family
ID=44114881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009273840A Active JP5203340B2 (ja) | 2009-12-01 | 2009-12-01 | 半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8716144B2 (ja) |
JP (1) | JP5203340B2 (ja) |
KR (1) | KR101295889B1 (ja) |
TW (1) | TWI445080B (ja) |
WO (1) | WO2011068029A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8416009B2 (en) * | 2011-07-13 | 2013-04-09 | International Business Machines Corporation | Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip |
JP2013084695A (ja) * | 2011-10-06 | 2013-05-09 | Tokyo Electron Ltd | 半導体装置の製造方法 |
TWI584374B (zh) * | 2012-09-18 | 2017-05-21 | Tokyo Electron Ltd | Plasma etching method and plasma etching device |
US8946076B2 (en) * | 2013-03-15 | 2015-02-03 | Micron Technology, Inc. | Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells |
KR20150015978A (ko) | 2013-08-02 | 2015-02-11 | 삼성디스플레이 주식회사 | 표시 장치의 방법 |
TWI593015B (zh) | 2014-07-10 | 2017-07-21 | 東京威力科創股份有限公司 | 基板之高精度蝕刻方法 |
JP2018170363A (ja) * | 2017-03-29 | 2018-11-01 | 東芝メモリ株式会社 | 半導体装置の製造方法及び半導体装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2734915B2 (ja) * | 1992-11-18 | 1998-04-02 | 株式会社デンソー | 半導体のドライエッチング方法 |
DE4241045C1 (de) | 1992-12-05 | 1994-05-26 | Bosch Gmbh Robert | Verfahren zum anisotropen Ätzen von Silicium |
US5976769A (en) * | 1995-07-14 | 1999-11-02 | Texas Instruments Incorporated | Intermediate layer lithography |
WO1999067817A1 (en) * | 1998-06-22 | 1999-12-29 | Applied Materials, Inc. | Silicon trench etching using silicon-containing precursors to reduce or avoid mask erosion |
KR100881472B1 (ko) * | 1999-02-04 | 2009-02-05 | 어플라이드 머티어리얼스, 인코포레이티드 | 소정 기판 상에 놓여져 있는 패턴화된 마스크 표면 위로 적층 구조물을 증착하기 위한 방법 |
US6303513B1 (en) * | 1999-06-07 | 2001-10-16 | Applied Materials, Inc. | Method for controlling a profile of a structure formed on a substrate |
US6318384B1 (en) * | 1999-09-24 | 2001-11-20 | Applied Materials, Inc. | Self cleaning method of forming deep trenches in silicon substrates |
AU2002367178A1 (en) * | 2001-12-27 | 2003-07-15 | Kabushiki Kaisha Toshiba | Etching method and plasma etching device |
US20070131652A1 (en) | 2003-01-12 | 2007-06-14 | Mitsuhiro Okune | Plasma etching method |
JP2006156467A (ja) * | 2004-11-25 | 2006-06-15 | Matsushita Electric Ind Co Ltd | プラズマエッチング方法 |
US7405162B2 (en) | 2004-09-22 | 2008-07-29 | Tokyo Electron Limited | Etching method and computer-readable storage medium |
JP4672318B2 (ja) * | 2004-09-22 | 2011-04-20 | 東京エレクトロン株式会社 | エッチング方法 |
US20060264054A1 (en) * | 2005-04-06 | 2006-11-23 | Gutsche Martin U | Method for etching a trench in a semiconductor substrate |
JP4653603B2 (ja) | 2005-09-13 | 2011-03-16 | 株式会社日立ハイテクノロジーズ | プラズマエッチング方法 |
JP4488999B2 (ja) * | 2005-10-07 | 2010-06-23 | 株式会社日立ハイテクノロジーズ | エッチング方法およびエッチング装置 |
US7902078B2 (en) | 2006-02-17 | 2011-03-08 | Tokyo Electron Limited | Processing method and plasma etching method |
JP4722725B2 (ja) * | 2006-02-17 | 2011-07-13 | 東京エレクトロン株式会社 | 処理方法およびプラズマエッチング方法 |
JP5124121B2 (ja) | 2006-10-02 | 2013-01-23 | 株式会社アルバック | ガラス基板のエッチング方法 |
JP5154260B2 (ja) * | 2008-02-26 | 2013-02-27 | パナソニック株式会社 | ドライエッチング方法及びドライエッチング装置 |
-
2009
- 2009-12-01 JP JP2009273840A patent/JP5203340B2/ja active Active
-
2010
- 2010-11-17 WO PCT/JP2010/070464 patent/WO2011068029A1/ja active Application Filing
- 2010-11-17 US US13/512,372 patent/US8716144B2/en active Active
- 2010-11-17 KR KR1020127013814A patent/KR101295889B1/ko active IP Right Grant
- 2010-11-30 TW TW099141327A patent/TWI445080B/zh active
Also Published As
Publication number | Publication date |
---|---|
KR101295889B1 (ko) | 2013-08-12 |
KR20120073365A (ko) | 2012-07-04 |
WO2011068029A1 (ja) | 2011-06-09 |
TW201137968A (en) | 2011-11-01 |
JP2011119359A (ja) | 2011-06-16 |
US20120238098A1 (en) | 2012-09-20 |
TWI445080B (zh) | 2014-07-11 |
US8716144B2 (en) | 2014-05-06 |
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