JP5171720B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5171720B2
JP5171720B2 JP2009095002A JP2009095002A JP5171720B2 JP 5171720 B2 JP5171720 B2 JP 5171720B2 JP 2009095002 A JP2009095002 A JP 2009095002A JP 2009095002 A JP2009095002 A JP 2009095002A JP 5171720 B2 JP5171720 B2 JP 5171720B2
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JP
Japan
Prior art keywords
wiring
wiring board
lead
region
layer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009095002A
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English (en)
Japanese (ja)
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JP2010245439A (ja
JP2010245439A5 (https=
Inventor
和之 中川
伸治 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009095002A priority Critical patent/JP5171720B2/ja
Publication of JP2010245439A publication Critical patent/JP2010245439A/ja
Publication of JP2010245439A5 publication Critical patent/JP2010245439A5/ja
Application granted granted Critical
Publication of JP5171720B2 publication Critical patent/JP5171720B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2009095002A 2009-04-09 2009-04-09 半導体装置 Expired - Fee Related JP5171720B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009095002A JP5171720B2 (ja) 2009-04-09 2009-04-09 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009095002A JP5171720B2 (ja) 2009-04-09 2009-04-09 半導体装置

Publications (3)

Publication Number Publication Date
JP2010245439A JP2010245439A (ja) 2010-10-28
JP2010245439A5 JP2010245439A5 (https=) 2012-04-26
JP5171720B2 true JP5171720B2 (ja) 2013-03-27

Family

ID=43098094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009095002A Expired - Fee Related JP5171720B2 (ja) 2009-04-09 2009-04-09 半導体装置

Country Status (1)

Country Link
JP (1) JP5171720B2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7413102B2 (ja) * 2020-03-17 2024-01-15 キオクシア株式会社 半導体装置
JP7570305B2 (ja) 2021-08-31 2024-10-21 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003282774A (ja) * 2002-03-25 2003-10-03 Kyocera Corp 配線基板およびその製造方法

Also Published As

Publication number Publication date
JP2010245439A (ja) 2010-10-28

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