JP5171720B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a stiffener ring is disposed so as to surround a semiconductor chip on the outer periphery of an upper surface of a wiring board on which the semiconductor chip is mounted.

  A semiconductor chip is flip-chip mounted on the upper surface of the package substrate, the bump electrode of the semiconductor chip is electrically connected to the land on the upper surface of the package substrate, and the connection portion between the bump electrode of the semiconductor chip and the land of the package substrate is underlined. A semiconductor device in the form of a semiconductor package is manufactured by sealing with a fill resin and connecting solder balls to the back surface of the package substrate.

  Japanese Patent Laying-Open No. 2005-136079 (Patent Document 1) describes a semiconductor device in which a reinforcing ring is arranged on the outer peripheral edge of a surface on which a semiconductor element of a wiring board is mounted.

  Japanese Patent Laying-Open No. 2005-244104 (Patent Document 2) describes a semiconductor device in which a reinforcing frame is installed on a surface of a wiring board so as to cover a mounting portion of an electronic component.

  Japanese Patent Application Laid-Open No. 11-74417 (Patent Document 3) describes a semiconductor device in which a ring is disposed between a BGA substrate on which a semiconductor chip is mounted and a heat spreader that dissipates heat from the semiconductor chip to the outside.

  International Patent Publication WO 2005/104230 pamphlet (Patent Document 4) describes a semiconductor device in which a stiffener is provided in a region surrounding a semiconductor chip on a package substrate.

JP 2005-136079 A JP-A-2005-244104 JP 11-74417 A International Patent Publication WO2005 / 104230 Pamphlet

  According to the study of the present inventor, the following has been found.

  When a semiconductor chip is flip-chip mounted on a package substrate, the heat dissipation path from the semiconductor chip to the package substrate becomes a bump electrode of the semiconductor chip, so when the entire back surface of the semiconductor chip is bonded to the package substrate like face-up bonding In comparison, it is difficult to dissipate heat from the semiconductor chip to the package substrate. For this reason, if the heat spreader is mounted on the back surface of the flip-chip mounted semiconductor chip, the heat generated in the semiconductor chip can be conducted to the heat spreader and radiated from the heat to the outside. However, if the heat spreader is bonded only to the backside of the semiconductor chip, the load on the semiconductor chip may increase due to external mechanical or thermal stress, which affects the mounting state of the semiconductor chip on the package substrate. May give. For this reason, if the stiffener ring is bonded and fixed to the outer periphery of the upper surface of the package substrate so as to surround the semiconductor chip, and the heat spreader is bonded to both the back surface of the semiconductor chip and the upper surface of the stiffener ring, mechanical or thermal from the outside Since the load applied to the semiconductor chip due to various stresses can be reduced, the mounting reliability of the semiconductor chip on the package substrate can be improved.

  Even when the heat spreader is not mounted, it is possible to suppress or prevent the package substrate from warping by adhering and fixing the stiffener ring so as to surround the semiconductor chip on the outer periphery of the upper surface of the package substrate. When a semiconductor chip is flip-chip mounted on a package substrate, the package substrate is likely to warp because the entire package substrate is not covered with a mold resin. When the package substrate is warped, the coplanarity of the solder ball is deteriorated and the mountability is lowered. In addition, if the package substrate is warped, it may adversely affect the mounting state when the semiconductor package is mounted on the mounting substrate, but stiffening prevents the package substrate from warping and improves solder ball coplanarity. By doing so, the mounting reliability of the semiconductor package can be improved.

  Thus, bonding the stiffener ring so as to surround the semiconductor chip on the outer periphery of the upper surface of the package substrate is a very useful technique.

  However, when a high-temperature high-humidity bias test under severe conditions was performed on a semiconductor device having a configuration in which a stiffener ring is fixed with an adhesive so as to surround the semiconductor chip on the outer periphery of the upper surface of the package substrate on which the semiconductor chip is mounted, It has been found by the inventor's investigation that Cu migration constituting the wiring of the package substrate is likely to occur in the region immediately below. This is because impurity ions contained in the adhesive that bonds the stiffener ring and the package substrate diffuse into the solder resist layer on the top layer of the package substrate during the high temperature and high humidity bias test under severe conditions. This is because the diffused solder resist is more likely to elute metal (metal constituting the wiring, that is, Cu) from the wiring in contact with the solder resist to the solder resist side as compared with the solder resist in other regions. For this reason, in the region immediately below the stiffener ring, impurities diffuse from the adhesive that adheres the stiffener ring to the solder resist layer, and the metal (Cu) constituting the wiring is likely to elute into the solder resist. Will be promoted. In the package substrate, if migration of Cu constituting the wiring is promoted, a short circuit (short circuit) defect or an open (disconnection) defect between the wirings may be caused, so that the reliability of the semiconductor device is lowered. This phenomenon was not observed in the high-temperature and high-humidity bias test at 85 ° C./85% RH, but in the high-temperature and high-humidity bias test performed under severe conditions such as 110 ° C./85% RH and 130 ° C./85% RH. Easy to manifest. In recent years, there are high demands for higher reliability of semiconductor devices, including semiconductor devices for in-vehicle use, and high reliability semiconductor devices that can withstand high-temperature, high-humidity bias tests performed under the severe conditions described above have been developed. It has been demanded.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In a semiconductor device according to a typical embodiment, a semiconductor chip is flip-chip mounted on an upper surface of a wiring board, and a stiffener ring is mounted on an outer periphery of the upper surface of the wiring board via an adhesive layer so as to surround the semiconductor chip. A plurality of external terminals are provided on the lower surface of the substrate, and the external terminals are also disposed immediately below the stiffener ring. A plurality of lead-out wirings for electrically connecting the plurality of first terminals on the upper surface of the wiring board to which the plurality of protruding electrodes of the semiconductor chip are respectively connected to the plurality of external terminals on the lower surface of the wiring board are provided. In the conductor layer of the same layer as the first terminal of the first terminal, it extends to a region on the inner peripheral side from a region immediately below the stiffener ring, but does not extend to a region immediately below the stiffener ring.

  Further, in a semiconductor device according to another typical embodiment, a semiconductor chip is flip-chip mounted on the upper surface of the wiring board, and stiffening is performed on the outer periphery of the upper surface of the wiring board via an adhesive layer so as to surround the semiconductor chip. A plurality of external terminals are provided on the lower surface of the wiring board. A plurality of lead-out wirings for electrically connecting the plurality of first terminals on the upper surface of the wiring board to which the plurality of protruding electrodes of the semiconductor chip are respectively connected to the plurality of external terminals on the lower surface of the wiring board are provided. In the same conductor layer as the first terminal of the first terminal, it extends to the region immediately below the stiffener ring, but the adhesive layer is not disposed immediately above the lead-out wiring.

  Further, in a semiconductor device according to another typical embodiment, a semiconductor chip is flip-chip mounted on the upper surface of the wiring board, and stiffening is performed on the outer periphery of the upper surface of the wiring board via an adhesive layer so as to surround the semiconductor chip. A plurality of external terminals are provided on the lower surface of the wiring board. A plurality of lead-out wirings for electrically connecting the plurality of first terminals on the upper surface of the wiring board to which the plurality of protruding electrodes of the semiconductor chip are respectively connected to the plurality of external terminals on the lower surface of the wiring board are provided. The conductor layer of the same layer as the first terminal also extends to a region immediately below the stiffener ring. The conductor layer of the same layer as the plurality of first terminals is provided with a conductor pattern to which a fixed potential is supplied around the lead-out wiring, and the lead-out wiring and the conductor in the region immediately below the adhesive layer. The distance between the patterns is wider than the distance between the lead-out wiring and the conductor pattern in the region other than directly below the adhesive layer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the reliability of the semiconductor device can be improved.

It is sectional drawing of the semiconductor device which is one embodiment of this invention. It is a top view of the semiconductor device which is one embodiment of the present invention. It is a bottom view of the semiconductor device which is one embodiment of the present invention. It is a plane perspective view of the semiconductor device which is one embodiment of the present invention. It is a plane perspective view of the semiconductor device which is one embodiment of the present invention. It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. It is a bottom view of the modification of the semiconductor device which is one embodiment of this invention. It is a principal part top view of the wiring board used for the semiconductor device which is one embodiment of this invention. It is a principal part top view of the wiring board used for the semiconductor device which is one embodiment of this invention. It is a principal part top view of the wiring board used for the semiconductor device which is one embodiment of this invention. It is a principal part top view of the wiring board which this inventor examined. It is a principal part top view of the wiring board which this inventor examined. It is a principal part top view of the modification of the wiring board used for the semiconductor device which is one embodiment of this invention. It is explanatory drawing which shows typically the capacitive coupling of extraction wiring. It is principal part sectional drawing of the modification of the semiconductor device which is one embodiment of this invention. FIG. 16 is a plan view of main parts of a wiring board used in the semiconductor device of FIG. 15. It is sectional drawing of the semiconductor device of other embodiment of this invention. FIG. 18 is a fragmentary cross-sectional view of the semiconductor device of FIG. 17. FIG. 18 is a plan view of main parts of a wiring board used in the semiconductor device of FIG. 17. FIG. 18 is a plan view of main parts of a wiring board used in the semiconductor device of FIG. 17. FIG. 18 is a plan view of main parts of a wiring board used in the semiconductor device of FIG. 17. It is sectional drawing of the semiconductor device of other embodiment of this invention. FIG. 23 is a fragmentary cross-sectional view of the semiconductor device of FIG. 22. FIG. 23 is a plan view of a principal part of a wiring board used in the semiconductor device of FIG. 22. FIG. 23 is a plan view of a principal part of a wiring board used in the semiconductor device of FIG. 22. FIG. 25 is a partially enlarged plan view of FIG. 24. It is a principal part top view of a wiring board when the space | interval between the wiring for a lead-out and a conductor pattern is made the same in all the area | regions of the upper surface of a wiring board. FIG. 23 is a plan view of relevant parts of a modification of the wiring board used in the semiconductor device of FIG. 22; It is sectional drawing in the manufacturing process of the semiconductor device of one embodiment of this invention. FIG. 30 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 29; FIG. 31 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 30; FIG. 32 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 31; FIG. 33 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 32; FIG. 34 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 33; FIG. 35 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 34;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
<Structure of semiconductor device>
A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

  1 is a cross-sectional view (overall cross-sectional view, side cross-sectional view) of a semiconductor device 1 according to an embodiment of the present invention, FIG. 2 is a top view (plan view) of the semiconductor device 1, and FIG. 1 is a bottom view (back view) of FIG. 4 is a top view (plan view) of the semiconductor device 1 when the heat spreader 7 and the adhesive layers 15a and 15b are seen through, and FIG. 5 is a perspective view of the stiffener ring 6 and the adhesive layer 14 in FIG. FIG. 6 is a top view (plan view) of the semiconductor device 1 at the time. The cross section of the semiconductor device 1 taken along the line A1-A1 in FIGS. 2 to 5 substantially corresponds to FIG. FIG. 6 is a main-portion cross-sectional view of the semiconductor device 1, and corresponds to a partially enlarged view of a region RE1 surrounded by a dotted line in FIG. Although FIG. 4 is a plan view, the semiconductor chip 3 and the stiffener ring 6 are hatched for easy viewing of the drawing.

  The semiconductor device 1 of the present embodiment shown in FIGS. 1 to 6 is a semiconductor device in the form of a semiconductor package.

  As shown in FIGS. 1 to 6, the semiconductor device 1 according to the present embodiment includes a wiring board 2, a semiconductor chip 3 mounted on the upper surface 2 a of the wiring board 2, a semiconductor chip 3, and the wiring board 2. A plurality of solder balls 5 provided on the lower surface 2b of the wiring substrate 2, a stiffener ring 6 mounted on the outer periphery of the upper surface 2a of the wiring substrate 2, the back surface 3b of the semiconductor chip 3, and A heat spreader 7 mounted on the upper surface 6a of the stiffener ring 6;

  The semiconductor chip 3 has a rectangular (quadrangle) planar shape that intersects its thickness. For example, after various semiconductor elements or semiconductor integrated circuits are formed on the main surface of a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like. The semiconductor substrate is manufactured by separating each semiconductor chip by dicing or the like.

  The semiconductor chip 3 has a front surface (second main surface) 3a which is a main surface on the semiconductor element formation side, and a back surface (second back surface) 3b which is a main surface opposite to the front surface 3a. A plurality of bump electrodes (projection electrodes, projection electrodes) 8 are formed on the surface 3 a of the chip 3. Accordingly, in the semiconductor chip 3, the main surface on the side where the bump electrodes 8 are formed becomes the surface 3 a of the semiconductor chip 3. Each bump electrode 8 of the semiconductor chip 3 is electrically connected to a semiconductor element or a semiconductor integrated circuit formed inside or on the surface layer of the semiconductor chip 3 via an internal wiring layer of the semiconductor chip 3 or the like. The bump electrode 8 is a protruding electrode and functions as a mounting electrode for flip-chip connection of the semiconductor chip 3 to the wiring board 2 and is made of, for example, a solder bump or a gold bump.

  The plurality of bump electrodes 8 are arranged in an area array on the entire surface 3a of the semiconductor chip 3, thereby increasing the number of terminals of the semiconductor chip due to higher functionality and reducing the size (reducing area) of the semiconductor chip. However, as another form, the plurality of bump electrodes 8 can be provided only on the peripheral portion (peripheral portion) of the surface 3 a of the semiconductor chip 3.

  The semiconductor chip 3 is flip-chip mounted on the upper surface 2 a of the wiring board 2. That is, the semiconductor chip 3 has the back surface 3b side of the semiconductor chip 3 facing upward, and the front surface 3a of the semiconductor chip 3 faces the upper surface 2a of the wiring substrate 2 with the plurality of bump electrodes 8 interposed therebetween. It is mounted (mounted) on the upper surface 2a. Therefore, the semiconductor chip 3 is face-down bonded to the upper surface 2 a of the wiring board 2.

  The plurality of bump electrodes 8 on the surface of the semiconductor chip 3 are respectively joined to the plurality of lands (terminals, substrate-side terminals, electrodes, conductive land portions) 9 on the upper surface 2 a of the wiring substrate 2. That is, the plurality of bump electrodes 8 on the surface of the semiconductor chip 3 are electrically and mechanically connected to the plurality of lands 9 on the upper surface 2a of the wiring board 2, respectively. Therefore, the semiconductor integrated circuit formed on the semiconductor chip 3 is electrically connected to the land 9 on the upper surface 2 a of the wiring substrate 2 via the bump electrode 8.

  A resin portion 4 as an underfill resin is filled between the semiconductor chip 3 and the upper surface 2 a of the wiring substrate 2. The resin portion 4 can buffer the burden on the bump electrode 8 due to the difference in thermal expansion coefficient between the semiconductor chip 3 and the wiring substrate 2. The resin part 4 consists of resin materials (for example, thermosetting resin material), such as an epoxy resin, for example, and can also contain a filler. As the filler of the resin part 4, silica or the like can be used.

  The wiring substrate (package substrate) 2 has a rectangular (quadrangle) planar shape that intersects its thickness, and has an upper surface (front surface, first main surface) 2a that is one main surface and a main surface opposite to the upper surface 2a. And a lower surface (back surface, first back surface) 2b. Of the upper surface 2 a of the wiring substrate 2, a chip mounting area (an area where the semiconductor chip 3 is mounted) has a plurality of lands 9 (or lands 9) in an arrangement corresponding to the arrangement of the bump electrodes 8 on the surface 3 a of the semiconductor chip 3. The upper protruding electrodes) are arranged (arranged). As a result, the semiconductor chip 3 is flip-chip mounted on the upper surface 2a of the wiring substrate 2, and a plurality of bump electrodes 8 on the surface 3a of the semiconductor chip 3 and a plurality of lands 9 (or on the lands 9) on the upper surface 2a of the wiring substrate 2 are mounted. Each of the protruding electrodes) can be bonded to each other. Reference numeral 3a denotes a chip mounting area on the upper surface 2a of the wiring board 2. The area on the upper surface 2a of the wiring board 2 where the semiconductor chip 3 is mounted, that is, the semiconductor chip 3 in the upper surface 2a of the wiring board 2 is planar. Corresponds to the area overlapping.

  The wiring board 2 is a multilayer wiring board (multilayer board) in which a plurality of insulator layers (dielectric layers) and a plurality of conductor layers (wiring layers, conductor pattern layers) are laminated and integrated, preferably build It can be produced by the up method. The land 9 on the upper surface 2a of the wiring board 2 is connected to the lower surface 2b of the wiring board 2 via the wiring (drawing wirings WR1, WR2, etc. described later) and vias (vias V1, V2, V3, etc. described later). The terminal 10 is electrically connected.

  In FIG. 6, four conductor layers (wiring layers, conductor pattern layers) M1, M2, M3, and M4 and three insulator layers (here, the insulating layer 11, the core layer 12, and the insulating layer 13) are alternately stacked. Although the wiring board 2 is formed, the number of insulator layers and conductor layers to be stacked is not limited to this, and can be variously changed as necessary.

  For example, as shown in FIG. 6, a conductor layer (wiring layer) is formed in order from the side closer to the core layer 12 on the upper surface of an insulating core layer (base material layer, insulating layer) 12 made of glass epoxy resin or the like. ) M2, an insulating layer 11 that is a build-up layer, and a conductor layer (wiring layer) M1 are formed (laminated). In addition, a conductor layer (wiring layer) M3, an insulating layer 13 as a build-up layer, and a conductor layer (wiring layer) M4 are formed on the lower surface of the core layer 12 in order from the side close to the core layer 12 ( Laminated). Accordingly, in the wiring board 2, the conductor layers M1 to M4 are arranged in the order of the conductor layer M1, the conductor layer M2, the conductor layer M3, and the conductor layer M4 from the upper surface 2a side to the lower surface 2b side. The conductor layers M1, M2, M3, and M4 are formed of a metal layer such as copper (Cu), for example, and are patterned into patterns as necessary. The insulating layers (build-up layers) 11 and 13 are formed of, for example, a resin material.

  The conductor layer (first wiring layer) M1 and the conductor layer (second wiring layer) M2 are electrically connected via a via V1 formed in the insulating layer 11 between the conductor layers M1 and M2, if necessary. Has been. In addition, the conductor layer (second wiring layer) M2 and the conductor layer (third wiring layer) M3 are electrically connected to each other through a via V2 formed in the core layer 12 between the conductor layers M2 and M3, if necessary. It is connected to the. The conductor layer (third wiring layer) M3 and the conductor layer (fourth wiring layer) M4 are electrically connected via a via V3 formed in the insulating layer 13 between the conductor layers M3 and M4, if necessary. It is connected to the.

  Here, the vias (vias V1, V2, V3) are holes (through holes) formed in the insulating layer constituting the wiring board, but a conductor film (conductor layer, wiring, via wiring) is formed on the side wall of the hole. Or the hole is filled with a conductor film (conductor layer, wiring, via wiring). In this application, a hole including this conductor film is referred to as a via (or via hole). And Therefore, the vias formed in the insulating layer constituting the wiring board are electrically connected between the conductor layers on the upper and lower surfaces of the insulating layer via the conductor film on the side wall of the hole constituting the via or in the hole. Can function to.

  In FIG. 6, the vias V1, V2, and V3 are shown in the case where the holes constituting the vias V1, V2, and V3 are filled with a conductor film. As another form, for example, a core layer The via V2 formed in 12 may be in a state in which the conductor film is formed on the side wall of the hole constituting the via V2 without completely filling the hole constituting the via V2 with the conductor film. .

  A plurality of lands 9 and a plurality of lead-out wirings (wirings) WR1 are formed on the upper surface 2a of the wiring substrate 2 by the uppermost conductor layer M1 of the plurality of conductor layers M1 to M4 included in the wiring substrate 2. . Therefore, the land 9 and the lead-out wiring WR1 are formed in the same layer using the same conductor material that constitutes the conductor layer M1. The land 9 functions as a terminal (substrate side terminal, electrode) for connecting the bump electrode 8 of the semiconductor chip 3, that is, a terminal for flip chip connection. One end of each lead wiring WR1 is integrally connected to each land 9, and on the upper surface 2a of the wiring board 2, the land 9 is drawn (drawn out) outside the region where the lands 9 are densely arranged. It can function as a wiring. A lead wire WR1 of the wiring layer M1 and a lead wire WR2 to be described later of the wiring layer M2 are a land 9 on the upper surface 2a of the wiring substrate 2 and a terminal 10 on the lower surface 2b of the wiring substrate 2 (and solder balls formed thereon). 5) is a wiring for electrically connecting to the signal, and is also a signal wiring for inputting or outputting a signal.

  A solder resist layer (solder resist layer, insulating layer, insulating film) SR1 made of an insulating layer is formed on the uppermost layer of the wiring board 2 (the uppermost layer on the upper surface 2a side, the outermost surface layer). It is exposed from the opening of solder resist layer SR1. On the other hand, the lead-out wiring WR1 is covered with the solder resist layer SR1. That is, on the upper surface 2a of the wiring board 2, the solder resist layer SR1 is formed on the insulating layer 11 so as to cover the conductor layer M1 other than the land 9, but the land 9 extends from the opening of the solder resist layer SR1. Exposed. For this reason, a later-described lead-out wiring WR1, land 16 and conductor pattern CP1 provided on the conductor layer M1 are covered with the solder resist layer SR1. By providing the solder resist layer SR1, it is possible to prevent the conductor layer M1 other than the land 9 from being exposed and short-circuited. The solder resist layer SR1 can also function as a protective film for the conductor layer M1 other than the land 9 (including the lead-out wiring WR1). Also, a plating film or a bump electrode (for example, a solder bump) can be formed on a portion of the land 9 exposed from the opening of the solder resist layer SR1, whereby the land 9 (or the bump electrode on the land 9) is formed. And the bump electrode 8 can be more accurately joined.

  In addition, a plurality of terminals (external connection terminals, electrodes, lands, conductive land portions) 10 are provided on the lower surface of the wiring board 2 by the lowermost conductor layer M4 among the plurality of conductor layers M1 to M4 of the wiring board 2. 2b. Accordingly, the terminal 10 is made of a conductor constituting the conductor layer M4. The terminal 10 functions as a terminal for connecting (arranging) the solder balls 5 as external terminals (external connection terminals) of the semiconductor device 1. A solder resist layer (solder resist layer, insulating layer, insulating film) SR2 made of an insulating layer is formed on the lowermost layer (uppermost layer on the lower surface 2b side) of the wiring board 2, and the terminal 10 is a solder resist layer SR2. It is exposed from the opening. Also, a plating film or a solder coat can be formed on a portion of the terminal 10 exposed from the opening of the solder resist layer SR2, so that the terminal 10 and the solder ball 5 can be joined more accurately. Become.

  On the lower surface 2 b of the wiring board 2, a plurality of terminals 10 are arranged in, for example, an array, and a solder ball (ball electrode, protruding electrode, protruding electrode) 5 is connected (formed) to each terminal 10 as an external electrode. Has been. For this reason, as shown in FIG. 3, a plurality of solder balls 5 are arranged on the lower surface 2b of the wiring board 2 in, for example, an array. The solder ball 5 can function as an external terminal (external connection terminal) of the semiconductor device 1. The plurality of lands 9 on the upper surface 2a of the wiring board 2 and the plurality of terminals 10 on the lower surface 2b of the wiring board 2 are electrically connected via the conductor layers M1 to M4 and the vias V1 to V3 of the wiring board 2. Therefore, the plurality of lands 9 on the upper surface 2a of the wiring board 2 and the plurality of solder balls 5 on the lower surface 2b of the wiring board 2 are electrically connected via the conductor layers M1 to M4 and the vias V1 to V3. Accordingly, each bump electrode 8 of the semiconductor chip 3 is bonded to each land 9 on the upper surface 2a of the wiring board 2, and further, the wiring board 2 is connected via the conductor layers M1 to M4 and vias V1 to V3 of the wiring board 2. It is electrically connected to each solder ball 5 on the lower surface 2b. 3 shows a case where a plurality of solder balls 5 are arranged in an array on the entire lower surface 2b of the wiring board 2, but as another form (modification), as shown in FIG. The solder balls 5 may be arranged in a single or a plurality of rows along the outer periphery of the lower surface 2 b of the wiring board 2 without arranging the solder balls 5 in the center of the lower surface 2 b of the wiring board 2.

  A stiffener ring (reinforcing member, ring member, frame body, reinforcing frame, reinforcing ring) 6 is disposed on the outer periphery of the upper surface 2a of the wiring board 2 with an adhesive layer (adhesive material) 14 so as to surround the semiconductor chip 3. Mounted (arranged, glued, fixed). As shown in FIG. 4, the stiffener ring 6 is a ring-shaped or frame-shaped member, and surrounds the semiconductor chip 3 planarly at a predetermined distance from the semiconductor chip 3 (that is, the upper surface of the wiring board 2). The semiconductor chip 3 is disposed along the outer periphery (periphery) of the upper surface 2a of the wiring board 2 so as to surround the semiconductor chip 3 when viewed in a plane parallel to 2a. The stiffener ring 6 is a reinforcing ring member for fixing the heat spreader 7.

  Since the stiffener ring 6 is disposed along the outer periphery (peripheral edge) of the upper surface 2 a of the wiring substrate 2, the planar outer shape of the stiffener ring 6 corresponds to the planar outer shape of the wiring substrate 2. For this reason, when the planar shape of the wiring board 2 is rectangular, the planar shape of the stiffener ring 6 is a ring shape (frame shape) whose outer shape and inner shape are rectangular.

  The lower surface 6b of the stiffener ring 6 is fixed by being bonded to the upper surface 2a of the wiring board 2 via the adhesive layer 14, and the upper surface 6a is fixed to the lower surface 7b of the heat spreader 7 via the adhesive layer 15a. It is glued. The stiffener ring 6 is a reinforcing ring member (reinforcing ring), and is provided to prevent the wiring board 2 from warping and to hold the heat spreader 7. For example, the stiffener ring 6 can be formed of a metal material such as copper (Cu) or a copper (Cu) alloy. A resin material (for example, a glass epoxy resin) can be used as the stiffener ring 6. From the viewpoint of the function of preventing the warping of the wiring board 2 by the stiffener ring 6, the stiffener ring 6 preferably has a property that is difficult to be deformed with respect to stress. It is more preferable if it has the desired properties.

  The adhesive 14 is obtained by curing a tape (film) type adhesive or a coating type adhesive, and is made of, for example, a thermosetting resin.

  A heat spreader (heat radiating member, heat radiating plate) 7 is bonded to the upper surface 6 a of the stiffener ring 6 via the adhesive layer (adhesive) 15 a and the adhesive layer (adhesive) to the back surface 3 b of the semiconductor chip 3. It is bonded via 15b. That is, the central region of the lower surface 7b of the heat spreader 7 is bonded to the back surface 3b of the semiconductor chip 3 via the adhesive layer 15b, and the outer peripheral region of the lower surface 7b of the heat spreader 7 is bonded to the upper surface 6a of the stiffener ring 6 via the adhesive layer 15a. As a result, the heat spreader 7 is fixed and held on both the semiconductor chip 3 and the stiffener ring 6. The heat spreader 7 conducts (dissipates) heat generated in the semiconductor chip 3 to the heat spreader 7, thereby suppressing the temperature rise of the semiconductor chip 3, and further dissipating heat from the heat spreader 7 to the outside of the semiconductor device 1. To work. Accordingly, the heat spreader 7 is a heat radiating member (heat radiating plate), for example, a plate-shaped heat radiating plate.

  The heat spreader 7 is preferably formed of a metal having high thermal conductivity, and can be formed of, for example, copper (Cu) or a copper (Cu) alloy. Further, if the stiffener ring 6 and the heat spreader 7 are formed of the same material (for example, copper), the coefficient of thermal expansion of the stiffener ring 6 and the heat spreader 7 becomes the same, which is more preferable. Warpage or the like can be suppressed or prevented.

  Unlike the present embodiment, when the stiffener ring 6 is not provided in the semiconductor device 1, the semiconductor device 1 tends to warp, and a mounting failure may occur during mounting on the mounting substrate. In particular, when the semiconductor chip 3 is flip-chip mounted on the wiring board 2, the wiring board 2 is likely to warp because the entire wiring board 2 is not covered with a mold resin. Further, as the external dimensions of the wiring board 2 increase with the increase in the number of terminals, the wiring board 2 is likely to warp. If the wiring substrate 2 is warped, there is a possibility that the mounting state of the semiconductor device 1 on the mounting substrate via the solder balls 5 is adversely affected. Further, when the stiffener ring 6 is not provided in the semiconductor device 1, the heat spreader 7 is bonded and held only to the semiconductor chip 3, so that the load on the semiconductor chip 3 increases and the semiconductor chip 3 There is a possibility of affecting the mounting state on the wiring board 2.

  On the other hand, by arranging the stiffener ring 6 on the upper surface 2a of the wiring board 2 as in the present embodiment, it is possible to suppress or prevent the wiring board 2 from being warped by the stiffener ring 6, and solder balls. The coplanarity of 5 can be improved, and the mountability and mounting reliability of the semiconductor device 1 on the mounting substrate can be improved. Further, the heat spreader 7 is bonded and fixed to both the back surface 3b of the semiconductor chip 3 and the upper surface 6a of the stiffener ring 6, so that the heat spreader 7 is externally attached as compared to the case where the heat spreader 7 is bonded only to the back surface 3b of the semiconductor chip 3. Since the load applied to the semiconductor chip 3 due to mechanical or thermal stress can be reduced, the mounting reliability of the semiconductor chip 3 on the wiring substrate 2 can be improved.

<About the issue>
However, when the present inventor examined a semiconductor device having a configuration in which a stiffener ring such as the above-described stiffener ring 6 is bonded to the upper surface of the wiring board with an adhesive, it has been found that the following problems occur.

That is, a high-temperature and high-humidity bias test under severe conditions was performed on a semiconductor device in which a stiffener ring was adhered to the outer periphery of the upper surface of a wiring board on which a semiconductor chip was mounted so as to surround the semiconductor chip. It has been found by the inventor's examination that migration of Cu constituting the wiring of the wiring board is likely to occur in the region immediately below the stiffener ring. This is because impurity ions (for example, Cl ⁻ , Br ⁻ , F ⁻ , SO, which are negative ions) included in the adhesive that bonds the stiffener ring and the wiring board during a severe high temperature and high humidity bias test. ₄ ^2- etc.) is caused by diffusion into the uppermost solder resist layer of the wiring board. The solder resist layer in the portion where the impurity ions from the adhesive diffused is in a state in which metal is more likely to elute from the wiring in contact with the solder resist layer to the solder resist layer than the solder resist layer in other regions. For this reason, the metal (here, Cu) constituting the wiring moves from the wiring located under the solder resist layer where the impurity ions from the adhesive are diffused and in contact with the solder resist layer to the solder resist layer side. It becomes easy to elute and Cu migration will be promoted. The occurrence of Cu migration is promoted in the wiring in contact with the solder resist layer in which impurity ions from the adhesive that adheres the stiffener ring are diffused. In the wiring board, if migration of Cu constituting the wiring is promoted, a short circuit (short circuit) defect or an open (disconnection) defect between the wirings may be caused, so that the reliability of the semiconductor device is lowered. This phenomenon was not observed in the high-temperature and high-humidity bias test at 85 ° C./85% RH, but in the high-temperature and high-humidity bias test performed under severe conditions such as 110 ° C./85% RH and 130 ° C./85% RH. Realize. In recent years, there are high demands for higher reliability of semiconductor devices, including semiconductor devices for in-vehicle use, and high reliability semiconductor devices that can withstand high-temperature, high-humidity bias tests performed under the severe conditions described above have been developed. It has been demanded.

  Therefore, by improving the adhesive that bonds the stiffener ring to the wiring board, the diffusion of impurity ions from the adhesive to the solder resist layer is prevented, thereby preventing the above phenomenon that Cu migration is promoted. However, various additives are added to the adhesive from the viewpoint of ease of handling, adhesive strength, and curing method, and the above phenomenon that Cu migration is promoted only by improving the adhesive. It is not easy to prevent. Therefore, in the present embodiment, the above phenomenon is countered by devising the structure of the wiring board 2 as follows.

<Features of wiring board>
FIG. 8 is a plan view of the main part of the wiring board 2 used in the semiconductor device 1 of the present embodiment, and the wiring board in a region substantially corresponding to the region RE2 surrounded by the dotted line in FIGS. 4 and 5 above. A plan view of 2 is shown. FIG. 8 shows a layout of the conductor layer M1 formed on the insulating layer 11 through the solder resist SR1. Actually, the conductor layer M1 in the region shown in FIG. 8 is covered with the solder resist SR1. Although FIG. 8 is a plan view, the conductor layer M1 is hatched for easy viewing of the drawing. Therefore, in FIG. 8, the hatched region corresponds to the region with the conductor layer M1, and the unhatched region corresponds to the region without the conductor layer M1. However, in FIG. 8, in order to make the drawing easy to see, hatching is changed between the lead-out wiring WR1 and the land 16, and the conductor pattern CP1, and this is the same in other plan views. FIG. 9 is a plan view of the main part of the wiring board 2 in the same plane area as that of FIG. 8, but not only the solder resist SR1 but also the conductor layer M1 and the insulating layer 11 are seen through and on the core layer 12. The layout of the formed conductor layer M2 is shown. Although FIG. 9 is a plan view, the conductor layer M2 is hatched to make the drawing easy to see. Therefore, FIG. 8 shows the pattern of the conductor layer M1, and FIG. 9 shows the pattern of the conductor layer M2. However, in order to simplify the understanding, FIG. The planar position of the lead-out wiring WR2 provided in the lower conductor layer M2 is indicated by a dotted line. In FIG. 9, the planar position of the lead-out wiring WR1 provided in the conductor layer M1 above the conductor layer M2 is indicated by a dotted line. It is. FIG. 10 is a plan view of the main part of the wiring board 2 in the same plane area as FIG. 8, but in FIG. 8, the plane area in which the adhesive layer 14 is arranged is shown with thick line hatching. Correspond. Similarly to FIG. 8, in FIG. 10, the planar position of the lead-out wiring WR2 provided in the conductor layer M2 is indicated by a dotted line. Further, in the present embodiment, since the entire lower surface 6b of the stiffener ring 6 is bonded to the upper surface 2a of the wiring board 2 via the adhesive layer 14, a planar region in which the adhesive layer 14 is disposed in FIG. And the plane area where the stiffener ring 6 is disposed is substantially the same.

  As shown in FIG. 1, FIG. 6 and FIG. 8, the uppermost conductor layer M1 of the plurality of conductor layers M1 to M4 constituting the wiring board 2 includes a plurality of lands 9, a plurality of lead-out wirings WR1, It has a plurality of lands 16 and a conductor pattern CP1.

  On the upper surface 2a of the wiring board 2, a plurality of lands 9 for connecting a plurality of bump electrodes 8 of the semiconductor chip 3 are arranged in a chip mounting area (an area immediately below the mounted semiconductor chip 3). The plurality of lands 9 need to be electrically connected to the plurality of terminals 10 (and the plurality of solder balls 5 respectively formed on the plurality of terminals 10) on the lower surface 2b of the wiring board 2.

  On the upper surface 2 a of the wiring board 2, the lands 9 that are flip chip connection terminals are densely arranged in the chip mounting area, whereas on the lower surface 2 b of the wiring board 2, the lands 9 are formed on the upper surface 2 a. The terminals 10 (and the solder balls 5 formed on the terminals 10) are arranged over an area wider than the arrangement area (that is, the entire lower surface 2b of the wiring board 2). For this reason, since the land 9 on the upper surface 2a of the wiring board 2 and the terminal 10 on the lower surface 2b are not arranged in a plane overlapping position, only vias (here, vias V1 to V3) provided in the wiring board 2 are provided. Thus, the land 9 on the upper surface 2a of the wiring board 2 and the terminal 10 on the lower surface 2b cannot be electrically connected. Therefore, in order to electrically connect the land 9 on the upper surface 2a of the wiring board 2 to the terminal 10 (solder ball 5) on the lower surface 2b, the lead-out wiring (provided in at least one of the wiring layers M1 to M4) In the wiring pattern, the land 9 needs to be drawn (drawn) in a direction parallel to the upper surface 2a and the lower surface 2b of the wiring board 2.

  Therefore, on the upper surface 2 a of the wiring board 2, the land 9 is a lead-out wiring WR 1 in the same layer as the land 9, and a position away from the area where the lands 9 are densely arranged immediately below the semiconductor chip 3 (land arrangement area). To the conductor layer M2 below the conductor layer M1 via the via V1 at a position away from the land arrangement region, and further via the vias V2 and V3 and the conductor layers M3 and M4. It is necessary to electrically connect to the terminal 10 made of the conductor layer M4. The lead-out wiring WR1 and the land 9 are provided in the conductor layer M1, and the land 9 and the lead-out wiring WR1 connected to the land 9 are integrally formed.

  Although not shown in FIG. 8 because it is out of the range of the region shown in FIG. 8, as can be seen from the cross-sectional view of FIG. 6, each of the lead-out wirings WR1 has a chip mounting region (mounted semiconductor). In the region immediately below the chip 3, one end is integrally connected to the land 9. As shown in FIG. 8, the other end of each of the lead-out wirings WR1 is located on the outer peripheral side (outer side) of the chip mounting area (the area directly below the semiconductor chip 3) in the upper surface 2a of the wiring board 2. The land 16 is integrally connected to the arranged land 16. That is, on the upper surface 2a of the wiring board 2, the land 9 arranged in the chip mounting area and the land 16 arranged in the outer peripheral area from the chip mounting area are electrically connected by the lead-out wiring WR1. It is connected to.

  Like the land 9 and the lead-out wiring WR1, the land 16 is also provided in the conductor layer M1, but the land 16 is not a flip-chip connection terminal, and the land 16 is covered with the solder resist layer SR1. The land 16 has a planar shape, for example, a circular shape, and its diameter is larger than the width of the lead-out wiring WR1. The land 16 can also be regarded as a part of the lead wiring WR1. The land 16 is electrically connected to the conductor layer M2 via a via V1 disposed under (directly below) the land 16, and further, the wiring board 2 via the vias V2, V3 and the conductor layers M3, M4. Are electrically connected to the terminal 10 on the lower surface 2b of the solder and the solder ball 5 connected thereon.

  On the upper surface 2a of the wiring board 2, a conductor pattern (conductor plane) CP1 to which a fixed potential is supplied is provided around the lead-out wiring WR1 (including the land 16). Similar to the lands 9 and 16 and the lead-out wiring WR1, the conductor pattern CP1 is also provided in the conductor layer M1. The fixed potential supplied to the conductor pattern CP1 is preferably a power supply potential or a ground potential. The conductor pattern CP1 is connected to the vias V1, V2, V3 and the conductor layers M2, M3 and the solder balls 5 for the power supply potential or the ground potential among the plurality of solder balls 5 arranged on the lower surface 2b of the wiring board 2. It is electrically connected via M4 (terminal 10). When the semiconductor device 1 is mounted on a mounting substrate (not shown), the power supply potential or ground potential solder balls 5 are connected to the power supply potential or ground potential terminals of the mounting substrate. Thereby, the power supply potential or the ground potential can be supplied from the solder ball 5 for the power supply potential or the ground potential to the conductor pattern CP1.

  The conductor pattern CP1 is formed on the entire upper surface 2a of the wiring board 2 and occupies a majority of the upper surface 2a of the wiring board 2, but the land 9 and 16 and the lead wiring WR1 are not in contact with each other. , 16 and the lead-out wiring WR1 are separated from each other by a predetermined distance. In the conductor layer M1, the conductor pattern CP1 to which a fixed potential is supplied is provided around the lead-out wiring WR1 so as to surround the lead-out wiring WR1, thereby improving the stability of the signal passing through the lead-out wiring WR1. it can. As with the lead-out wiring WR1 and the land 16, the conductor pattern CP1 is also covered with the solder resist layer SR1. Also, since the lands 9 are densely packed in the chip mounting area (the area immediately below the semiconductor chip 3) on the upper surface 2a of the wiring board 2, the conductor pattern CP1 need not be formed.

  The conductor pattern CP1 has a larger area than the lands 9 and 16 and the lead-out wiring WR1, and is formed over the entire upper surface 2a of the wiring board 2 (excluding the chip mounting region). Therefore, a large number (a plurality of) degas holes (for degassing) are provided in the conductor pattern CP1 so that the gas generated from the insulating layers 11 and 13 and the core layer 12 can be easily released through the conductor layer M1 when the wiring board 2 is manufactured. Hole) DH is formed. The degas hole DH is a portion without the conductor pattern CP1 (conductor layer M1) in the plane of the conductor pattern CP1, and the planar shape thereof is, for example, a circular shape. Although it is more preferable to provide the degas hole DH in the conductor pattern CP1, the formation of the degas hole DH can be omitted if there is no problem in degassing.

  When the stiffener ring 6 is bonded to the upper surface 2a of the wiring board 2 via the adhesive layer 14, the adhesive layer 14 is disposed on the solder resist layer SR1 that is the uppermost layer of the wiring board 2. As described above, in a high-temperature and high-humidity bias test under severe conditions, impurity ions contained in the adhesive layer 14 diffuse into the solder resist layer SR1 in a region in contact with the adhesive layer 14. When the conductor layer M1 is in contact with the solder resist layer SR1 in the region where impurity ions are diffused from the adhesive layer 14, the metal (Cu in this case) constituting the conductor layer M1 is eluted from the conductor layer M1 to the solder resist layer SR1. It's easy to do. Therefore, in the present embodiment, as can be seen by comparing FIG. 8 and FIG. 10, it is located under the solder resist layer SR1 in a region located under the adhesive layer 14 and capable of diffusing impurity ions from the adhesive layer 14. The lead wire WR1 and the land 16 are not arranged.

  That is, in the present embodiment, the lead-out wiring WR1 and the land 16 do not exist in the region immediately below the stiffener ring 6 on the upper surface 2a of the wiring board 2, and thereby, on the upper surface 2a of the wiring board 2. The lead-out wiring WR1 and the land 16 can be prevented from being present in the region immediately below the adhesive layer 14. In other words, the plurality of lead-out wirings WR1 provided on the upper surface 2a of the wiring board 2 extend to a region on the inner peripheral side with respect to the region immediately below the stiffener ring 6 (adhesive layer 14) (formation). It does not extend (is not formed) in the region immediately below the stiffener ring 6 (adhesive layer 14). Further, the land 16 is disposed in a region on the inner peripheral side from a region immediately below the stiffener ring 6 (adhesive layer 14), and is disposed in a region immediately below the stiffener ring 6 (adhesive layer 14). Absent.

  Note that the region immediately below the stiffener ring 6 corresponds to a region that overlaps the stiffener ring 6 when viewed in a plane parallel to the upper surface 2 a of the wiring board 2. Further, the region immediately below the adhesive layer 14 corresponds to a region that overlaps the adhesive layer 14 in a plan view when viewed in a plane parallel to the upper surface 2 a of the wiring substrate 2. Further, the region on the inner peripheral side with respect to the region directly below the stiffener ring 6 is located on the inner side of the region overlapping the stiffener ring 6 in a plane parallel to the upper surface 2a of the wiring board 2 (on the semiconductor chip 3). This corresponds to the area near the center. Further, the region on the inner peripheral side with respect to the region directly below the adhesive layer 14 is located on the inner side (semiconductor chip) with respect to the region overlapping the adhesive layer 14 in a plane when viewed in a plane parallel to the upper surface 2a of the wiring board 2. 3 corresponds to the region near the center of 3). Further, the region other than just below the stiffener ring 6 corresponds to a region that does not overlap with the stiffener ring 6 when viewed in a plane parallel to the upper surface 2 a of the wiring board 2. Further, the region other than directly below the adhesive layer 14 corresponds to a region that does not overlap the adhesive layer 14 in a plan view when viewed in a plane parallel to the upper surface 2 a of the wiring substrate 2.

  Unlike the present embodiment, when the terminal 10 (solder ball 5) is not formed in the region directly under the stiffener ring 6 on the lower surface 2b of the wiring board 2, the land 9 is directly under the stiffener ring 6 with a lead-out wiring. The land 9 and the terminal 10 (solder ball 5) can be electrically connected without being routed to the region.

  However, in this embodiment, as can be seen from FIG. 1, FIG. 3, FIG. 4 and FIG. 6, on the lower surface 2b of the wiring board 2, there are a plurality of terminals 10 and their upper portions in the region directly under the stiffener ring 6. A plurality of solder balls 5 formed in the above are disposed. That is, the terminals 10 and the solder balls 5 are also arranged at positions that overlap the stiffener ring 6 when viewed in a plane parallel to the upper surface 2 a and the lower surface 2 b of the wiring board 2. As described above, it is more advantageous for the semiconductor device 1 to have multiple terminals and to be miniaturized (smaller area) when the terminals 10 and the solder balls 5 are also arranged at positions overlapping the stiffener ring 6 in plan view. . However, in this case, in order to electrically connect the land 9 to the solder ball 5 connection terminal 10 located in the region immediately below the stiffener ring 6, the flip-chip connection land 9 is connected by a lead wiring. It is necessary to route to the area immediately below the stiffener ring 6.

  Therefore, in the present embodiment, in order to electrically connect the land 9 to the terminal 10 for connecting the solder ball 5 located in the region immediately below the stiffener ring 6, the land 9 is connected to the stiffener only by the lead wiring WR1. The land 9 is routed to the region immediately below the stiffener ring 6 by using the lead-out wiring WR1 and the lead-out wiring WR2 instead of being routed to the region directly below the ring 6. That is, the lead-out wiring (wiring) WR1 composed of the uppermost conductor layer M1 among the plurality of conductor layers M1 to M4 constituting the wiring board 2 is not extended to the region immediately below the stiffener ring 6 (adhesive layer 14). Without extending, the land 16 is arranged in front of the region immediately below the stiffener ring 6 (adhesive layer 14) (land 9 side). Instead, the land 16 is provided on the conductor layer M2 and via the via V1. A lead-out wiring (wiring) WR2 electrically connected to the land 16 is extended to a region immediately below the stiffener ring 6 (adhesive layer 14).

  Specifically, as can be seen from FIGS. 6 and 8 to 10, the conductor is provided directly below the land 16 disposed in the region on the inner peripheral side of the region immediately below the stiffener ring 6 (adhesive layer 14). The land 17 provided in the layer M2 is disposed, the land 16 and the land 17 are electrically connected by the via V1, and the lead wiring WR2 whose one end is integrally connected to the land 17 is connected to the stiffener ring 6 ( It extends to the region immediately below the adhesive layer 14). The other end of the lead-out wiring WR2 is integrally connected to a land 18 provided in the conductor layer M2 and disposed in a region immediately below the stiffener ring 6 (adhesive layer 14). That is, in the conductor layer M2 of the wiring board 2, the land 17 disposed in a region on the inner peripheral side with respect to the region immediately below the stiffener ring 6 (adhesive layer 14) and the region directly below the stiffener ring 6 (adhesive layer 14). The land 18 arranged in this area is electrically connected through the lead-out wiring WR2.

  The via V1 that electrically connects the lead-out wiring WR1 and the lead-out wiring WR2, that is, the via V1 between the land 16 and the land 17 is disposed on the land 17 directly below the land 16, Similarly to 17, it is arranged in a region on the inner peripheral side with respect to the region immediately below the stiffener ring 6 (adhesive layer 14). The land 17 and the land 18 have a planar shape, for example, a circular shape, and the diameter thereof is larger than the width of the lead-out wiring WR2. The land 18 disposed in the region immediately below the stiffener ring 6 (adhesive layer 14) is electrically connected to the conductor layer M3 via the via V2 disposed immediately below the land 18, and further includes the via V3 and the via V3. The conductor layer M4 is electrically connected to the terminals 10 on the lower surface 2b of the wiring board 2 arranged immediately below the stiffener ring 6 and the solder balls 5 connected thereon. The lands 17 and 18 can also be regarded as a part of the lead wiring WR2.

  As described above, in the present embodiment, the solder balls 5 arranged in the region immediately below the stiffener ring 6 are provided on the conductor layer M2 from the region immediately below the stiffener ring 6 to the region immediately below the stiffener ring 6. Electrically connected to the land 9 via the lead-out wiring WR2 extending to the inner peripheral region and the lead-out wiring WR1 extending to the inner peripheral region from the region directly below the stiffener ring 6 It is doing.

  FIGS. 11 and 12 are plan views of the principal part of the wiring board 102 which is a premise for the study of the present embodiment, and correspond to FIGS. 8 and 10 respectively. However, what is indicated by the dotted line in FIG. 10 is the planar position of the lead-out wiring WR2, but what is indicated by the dotted line in FIG. 12 is the lead-out wiring WR1 located below the adhesive layer 14. The plane position.

  In the wiring board 102 examined by the present inventor shown in FIG. 11 and FIG. 12, in order to electrically connect the land 9 to the terminal 10 for connecting the solder ball 5 located in the region immediately below the stiffener ring 6, The land 9 is routed to the region immediately below the stiffener ring 6 only by the lead wiring WR1. That is, in the wiring substrate 102, the lead-out wiring WR1 made of the uppermost conductor layer M1 is extended to a region immediately below the adhesive layer 14.

  Therefore, when the wiring board 102 shown in FIGS. 11 and 12 is used instead of the wiring board 2 of the present embodiment, the adhesive layer 14 is used in the high-temperature and high-humidity bias test under severe conditions as described above. When the impurity ions contained therein diffuse into the solder resist layer SR1, the lead wiring WR1 in the portion indicated by the dotted line in FIG. 12 (the portion located immediately below the adhesive layer 14) has Cu migration. It tends to occur. For this reason, when the wiring substrate 102 is used, in the high-temperature and high-humidity bias test under severe conditions as described above, the lead-out wiring of the portion indicated by the dotted line in FIG. 12 (the portion located in the region immediately below the adhesive layer 14) There is a possibility that WR1 is disconnected or the lead-out wiring WR1 in a portion indicated by a dotted line in FIG. 12 (portion located in a region immediately below the adhesive layer 14) is short-circuited with the conductor pattern CP1.

  On the other hand, in this embodiment, as can be seen from FIGS. 8 and 10, the lead-out wiring WR1 and the land 16 are arranged in the region directly below the adhesive layer 14 on the upper surface 2a of the wiring board 2. Not. That is, the lead-out wiring WR1 and the land 16 are not arranged in the region immediately below the stiffener ring 6 on the upper surface 2a of the wiring board 2. For this reason, even if the impurity ions contained in the adhesive layer 14 diffuse into the solder resist layer SR1 in the high-temperature and high-humidity bias test under severe conditions as described above, the portion where the impurity ions diffuse (adhesive layer) The lead wiring WR1 and the land 16 are not arranged immediately below the solder resist layer SR1. Accordingly, the elution of metal (here, Cu) from the lead wiring WR1 and the land 16 to the solder resist layer SR1 can be suppressed or prevented, and Cu migration can be suppressed or prevented. Therefore, disconnection of the lead-out wiring WR1 and a short circuit between the lead-out wiring WR1 and the conductor pattern CP1 can be prevented, and the reliability of the semiconductor device can be improved.

  Further, the lead-out wiring WR2 provided in the conductor layer M2 below the conductor layer M1 extends also to the region immediately below the stiffener ring 6, and therefore is also disposed immediately below the adhesive layer 14. However, the lead-out wiring WR2 is not in contact with the solder resist layer SR1, and the insulating layer 11 is interposed between the solder resist layer SR1 and the lead-out wiring WR2. As described above, when a high-temperature and high-humidity bias test under severe conditions is performed, the impurity ions contained in the adhesive layer 14 can diffuse into the solder resist layer SR1, but further pass through the solder resist layer SR1 for insulation. There is little diffusion even into the layer 11, and the impurity ions contained in the adhesive layer 14 are less likely to reach the portion of the insulating layer 11 that is in contact with the lead-out wiring WR <b> 2. For this reason, even if the lead-out wiring WR2 of the conductor layer M2 is arranged immediately below the adhesive layer 14, the metal (Cu here) constituting the lead-out wiring WR2 is transferred to the insulating layer 11 and the solder resist layer SR1. Since it does not elute, disconnection of the lead-out wiring WR2 or a short circuit between the lead-out wiring WR2 and a conductor pattern CP2 described later does not occur.

  In the present embodiment, the lead-out wiring WR2 provided in the conductor layer M2 that is not the uppermost conductor layer M1 among the plurality of conductor layers M1 to M4 constituting the wiring board 2 is connected to the adhesive layer 14 (that is, It extends from the region immediately below the stiffener ring 6) to the region on the inner peripheral side of the region immediately below the adhesive layer 14 (that is, the stiffener ring 6). Then, via the lead-out wiring WR2 and the lead-out wiring WR1 extending to the inner peripheral side region from the region directly below the adhesive layer 14 (ie, the stiffener ring), the lower surface 2b of the wiring board 2 is provided. The terminal 10 (and the solder ball 5 connected thereto) can be electrically connected to the land 9 on the upper surface 2 a of the wiring board 2. Therefore, the terminal 10 (and the solder ball 5 formed thereon) electrically connected to the land 9 on the upper surface 2a of the wiring board 2 via the lead-out wirings WR1 and WR2 is connected to the lower surface of the wiring board 2. In 2b, it can be arranged in the region directly under the stiffener ring 6. Thereby, the multi-terminal and miniaturization (area reduction) of the semiconductor device 1 can be achieved.

  Further, it is preferable that the lead-out wiring WR1 and the land 16 be separated from the region immediately below the adhesive layer 14 by 100 μm or more in a direction parallel to the upper surface 2a of the wiring board 2. That is, not only the region immediately below the adhesive layer 14 but also the region within 100 μm from the region immediately below the adhesive layer 14 in the direction parallel to the upper surface 2a of the wiring board 2 includes the lead-out wiring WR1 and the land 16. It is preferable that they are not arranged. In other words, it is preferable that the plane distance between the lead wiring WR1 and the land 16 and the adhesive layer 14 (distance when viewed in a plane parallel to the upper surface 2a of the wiring substrate 2) is 100 μm or more. The distance L1 shown in FIG. 10 is preferably 100 μm or more (L1 ≧ 100 μm).

  As described above, in the high-temperature and high-humidity bias test under severe conditions, impurity ions contained in the adhesive layer 14 may diffuse in the solder resist layer SR1 in the lateral direction, but the diffusion distance is several tens of μm. It is estimated to be about the following. For this reason, if the lead-out wiring WR1 and the land 16 are separated from the region immediately below the adhesive layer 14 by 100 μm or more in a direction parallel to the upper surface 2a of the wiring board 2, the lead-out wiring WR1 and the land 16 are positioned directly above. Impurities from the adhesive layer 14 cannot diffuse into the partial solder resist layer SR1. For this reason, the elution of the metal (here, Cu) from the lead wiring WR1 and the land 16 to the solder resist layer SR1 can be prevented more accurately, the disconnection of the lead wiring WR1, the lead wiring WR1 and the conductor pattern. A short circuit with CP1 can be prevented more accurately. Therefore, the reliability of the semiconductor device can be further improved.

  FIG. 13 is a plan view of an essential part showing a modification of the wiring board 2 and corresponds to FIG. Similar to FIG. 9, FIG. 13 shows a layout of the conductor layer M2 formed on the core layer 12, and FIG. 13 is a plan view, but the conductor layer M2 is shown in order to make the drawing easier to see. Is hatched, and the planar position of the lead-out wiring WR1 provided in the conductor layer M1 above the conductor layer M2 is indicated by a dotted line.

  As shown in FIG. 13, also in the conductor layer M2 of the wiring board 2, the lead-out wiring WR2 (including the lands 17 and 18) is surrounded around the lead-out wiring WR2 (including the lands 17 and 18). A conductor pattern (conductor plane) CP2 to which a fixed potential is supplied can also be provided. As an example, the conductor pattern CP2 is electrically connected to the conductor pattern CP1 of the conductor layer M1 through the via V1, and preferably a power supply potential or a ground potential is supplied as a fixed potential. The conductor pattern CP2 is formed on the entire top surface of the core layer 12 and occupies the majority of the top surface of the core layer 12, but the lands 17, 18 are not in contact with the lands 17, 18 and the lead-out wiring WR2. And a predetermined distance from the lead-out wiring WR2. In the conductor layer M2, by providing the conductor pattern CP2 to which a fixed potential is supplied around the lead-out wiring WR2, the stability of the signal passing through the lead-out wiring WR2 can be improved. Further, in the same manner that a large number (a plurality of) degas holes DH are provided in the conductor pattern CP1 of the conductor layer M1, a large number (a plurality of) degas holes DH (not shown in FIG. 13) are provided in the conductor pattern CP2 of the conductor layer M2. It can also be provided.

  FIG. 14 is an explanatory diagram schematically showing capacitive coupling of the lead-out wiring WR2.

  In the semiconductor device 1 according to the present embodiment, as shown in FIGS. 6 and 8, the conductor pattern CP1 to which a fixed potential is supplied is also formed in the region immediately below the stiffener ring 6 in the wiring board 2. doing. For this reason, as shown in FIG. 14, the lead-out wiring WR2 of the conductor layer M2 is not only capacitively coupled with the conductor pattern CP2 of the same layer and the conductor pattern of the lower conductor layer M3, but also the upper conductor layer. It is also capacitively coupled to the conductor pattern CP1 of M1. For this reason, even if the stiffener ring 6 is formed of a metal material, the conductor pattern CP1 is interposed between the stiffener ring 6 and the lead-out wiring WR2, so that the case where the conductor pattern CP1 is not interposed is present. The influence of capacitive coupling between the stiffener ring 6 and the lead-out wiring WR2 can be suppressed.

  For this reason, in the wiring board 2, it is more preferable that the conductor pattern CP1 is also formed in a region immediately below the stiffener ring 6, so that the impedance of the inner layer wiring (including the lead-out wiring WR2) of the wiring board 2 can be increased. It can be designed to match.

  The conductor pattern CP1 is a conductor pattern to which a fixed potential (preferably a power supply potential or a ground potential) is supplied, and is formed over the entire region immediately below the stiffener ring 6. For this reason, even in the high-temperature and high-humidity bias test under severe conditions as described above, the impurity ions contained in the adhesive layer 14 diffuse into the solder resist layer SR1, thereby forming the metal (here, the conductor pattern CP1). In this case, even if Cu) is eluted to the solder resist layer SR1, the conductor pattern CP1 does not suffer from defects such as disconnection or short circuit, so the reliability does not decrease.

  FIG. 15 is a cross-sectional view of a main part of a modified example of the semiconductor device 1 of the present embodiment, and corresponds to FIG. 6 of the first embodiment. FIG. 16 is a plan view of an essential part of the wiring board 2 used in the semiconductor device 1 according to the modification of FIG. 15, and corresponds to FIG. Similar to FIG. 8 above, FIG. 16 shows a layout of the conductor layer M1 formed on the insulating layer 11, and FIG. 16 is a plan view. M1 is hatched, and the planar position of the lead-out wiring WR2 provided in the conductor layer M2 below the conductor layer M1 is indicated by a dotted line.

  In the semiconductor device 1 of the modified example of FIG. 15, as shown in FIGS. 15 and 16, the conductor pattern CP <b> 1 to which a fixed potential is supplied is disposed on the wiring board 2 in the region immediately below the stiffener ring 6. Although it is formed in the peripheral region, it is not formed in the region immediately below the stiffener ring 6. Even in the semiconductor device 1 of the modification of FIG. 15, the effect of suppressing or preventing the elution of metal (here, Cu) from the lead wiring WR1 and the land 16 to the solder resist layer SR1 is the same. Disconnection of the wiring WR1 and a short circuit between the lead-out wiring WR1 and the conductor pattern CP1 can be prevented, and the reliability of the semiconductor device can be improved.

  In the present embodiment, the semiconductor device 1 using the heat spreader 7 has been described. However, as another embodiment, the heat spreader 7 can be omitted (in this case, the adhesive layers 15a and 15b are also omitted). When the heat spreader 7 is used, the stiffener ring 6 has a function of preventing warping of the wiring board 2 and holding the heat spreader 7, and the necessity and usefulness of the stiffener ring 6 is very large. Even when is omitted, the stiffener ring 6 is useful because it has a function of preventing the wiring board 2 from warping. Even when the heat spreader 7 is omitted, when the stiffener ring 6 is bonded to the wiring board with an adhesive, the above-described problem that Cu migration is promoted in the high-temperature and high-humidity bias test under the above-mentioned severe conditions. Therefore, by applying this embodiment, the above problems can be solved and the reliability of the semiconductor device can be improved. That is, this embodiment is effective when the stiffener ring 6 is bonded to the wiring board with an adhesive. The same applies to the following second to fourth embodiments.

  In the present embodiment, the description has been given of the case where the lead-out wiring WR2 extending from the region immediately below the stiffener ring 6 to the region on the inner peripheral side of the region directly below the stiffener ring 6 is provided in the conductor layer M2. As another form, the lead-out wiring WR2 extending from the region immediately below the stiffener ring 6 to the region on the inner peripheral side of the region directly below the stiffener ring 6 can be provided in the conductor layer M3 or the conductor layer M4. . That is, the lead-out wiring WR2 extending from the region immediately below the stiffener ring 6 to the region on the inner peripheral side of the region directly below the stiffener ring 6 is provided on any of the conductor layers M2, M3, and M4 other than the conductor layer M1. Can be provided. For this reason, the solder balls 5 (terminals 10) arranged in the region immediately below the stiffener ring 6 are directly below the stiffener ring 6 in one or more of the conductor layers M2, M3, M4 other than the conductor layer M1. The region is routed (drawn) from the region to the region on the inner peripheral side than the region directly below the stiffener ring 6, and this is routed through the lead-out wiring WR1 extending to the region on the inner peripheral side from the region directly below the stiffener ring 6. The land 9 can be electrically connected.

  In the present embodiment, the semiconductor chip 3 is flip-chip mounted on the upper surface 2 a of the wiring substrate 2, and the plurality of bump electrodes 8 on the surface 3 a of the semiconductor chip 3 and the plurality of lands 9 on the upper surface 2 a of the wiring substrate 2 Are electrically connected to each other. This is not only the case where each bump electrode 8 of the semiconductor chip 3 is directly connected to each land 9 of the wiring board 2 but also a protruding electrode (for example, solder) on each land 9 of the wiring board 2 before the semiconductor chip 3 is mounted. It is assumed that the bump electrode 8 of the semiconductor chip 3 is connected to the bump electrode on the land 9 in advance. The same applies to the following second to fourth embodiments.

(Embodiment 2)
17 is a cross-sectional view (overall cross-sectional view, side cross-sectional view) of the semiconductor device 1a of the present embodiment, and FIG. 18 is a cross-sectional view of the main part of the semiconductor device 1a. This corresponds to FIG. FIG. 19 is a plan view of an essential part of the wiring board 2 used in the semiconductor device 1a of the present embodiment, and corresponds to FIG. Similarly to FIG. 8 described above, FIG. 19 shows a layout of the conductor layer M1 formed on the insulating layer 11 through the solder resist layer SR1, and FIG. 19 is a plan view. In order to make it easier to see, the conductor layer M1 is hatched. Actually, the conductor layer M1 in the region shown in FIG. 19 is covered with the solder resist SR1. FIG. 20 is a plan view of the main part of the wiring board 2 in the same plane area as FIG. 19, but in FIG. 19, the plane area where the adhesive layer 14 is arranged is indicated by thick line hatching. This corresponds to FIG. 10 of the first embodiment. FIG. 21 is a plan view of the main part of the wiring board 2 in the same plane area as in FIGS. 18 and 19. In FIG. 19, the plane area where the stiffener ring 6 is arranged is hatched with fine lines. Corresponds to what is shown. In FIG. 21, the planar position of the lead-out wiring WR1 located under the stiffener ring 6 is indicated by a dotted line, and the planar position of the adhesive layer 14 located under the stiffener ring 6 is indicated by a broken line. Accordingly, FIGS. 19 to 21 are all seen through the solder resist layer SR1, but the structure in which the stiffener ring 6 is removed from FIG. 21 corresponds to FIG. 20, and the adhesive layer 14 is further removed from FIG. This corresponds to FIG.

  In the semiconductor device 1 of the first embodiment, the lead-out wiring WR1 is not arranged in the region immediately below the stiffener ring 6. On the other hand, in the semiconductor device 1a of the present embodiment, unlike the first embodiment, at least a part of the plurality of lead-out wirings WR1 provided on the upper surface 2a of the wiring substrate 2 is the stiffener ring 6. It extends (forms or is placed) directly under the area. That is, as can be seen from a comparison between FIG. 19 and FIG. 11, the wiring board 2 used in the semiconductor device 1a according to the present embodiment has a conductor layer M1 having a conductor layout in the wiring board 102 of FIG. The layout is the same as that of the layer M1. In order to solve the problem described in the first embodiment, the lead-out wirings WR1 and WR2 are devised in the first embodiment. However, in the present embodiment, the planar layout of the adhesive layer 14 is devised. ing.

  That is, in the semiconductor device 1 of the first embodiment, since the entire lower surface 6b of the stiffener ring 6 is bonded to the upper surface 2a of the wiring board 2 via the adhesive layer 14, the adhesive layer in FIG. The plane area in which 14 is arranged and the plane area in which the stiffener ring 6 is arranged are substantially the same. However, in the semiconductor device 1a of the present embodiment, since the lead-out wiring WR1 is also arranged in the region immediately below the stiffener ring 6, unlike the present embodiment, if the entire lower surface 6b of the stiffener ring 6 is When bonded to the upper surface 2 a of the wiring substrate 2 via the adhesive layer 14, the lead-out wiring WR 1 is also disposed in the region immediately below the adhesive layer 14. Therefore, in the semiconductor device 1a of the present embodiment, the entire lower surface 6b of the stiffener ring 6 is not bonded to the upper surface 2a of the wiring board 2 via the adhesive layer 14, but is a region immediately below the stiffener ring 6. In addition, the adhesive layer 14 is not disposed immediately above the lead-out wiring WR1.

  Specifically, as shown in FIGS. 17 and 18, the portion where the adhesive layer 14 is interposed and the adhesive layer 14 are not interposed between the lower surface 6 b of the stiffener ring 6 and the upper surface 2 a of the wiring substrate 2. As can be seen from FIG. 20, the adhesive layer 14 is disposed on the upper surface 2a of the wiring board 2 so as to avoid the region immediately above the lead-out wiring WR1, and the top of the lead-out wiring WR1 is bonded. The material layer 14 is not interposed.

  In other words, as can be seen by comparing FIG. 20 and FIG. 21, the region immediately below the stiffener ring 6 includes a region where the adhesive layer 14 is disposed and a region where the adhesive layer 14 is not disposed. is there. The lead-out wiring WR1 extends directly under the stiffener ring 6 and directly under the area where the adhesive layer 14 is not disposed. However, the lead-out wiring WR1 is in the area immediately below the stiffener ring 6 and the adhesive layer. It is not formed immediately below the region where 14 is arranged.

  The other configuration of the semiconductor device 1a according to the present embodiment is almost the same as that of the semiconductor device 1 according to the first embodiment, and therefore the description thereof is omitted here.

  In the present embodiment, the lead-out wiring WR1 and the land 16 are also present in the region immediately below the stiffener ring 6, but the lead-out wiring WR1 and the land 16 are not present in the region immediately below the adhesive layer 14. ing. That is, when viewed in a plane parallel to the upper surface 2a of the wiring substrate 2, the lead-out wiring WR1 and the adhesive layer 14 do not overlap in a plane. Therefore, as described above, even if the impurity ions contained in the adhesive layer 14 diffuse into the solder resist layer SR1 in the severe high-temperature and high-humidity bias test, the portion where the impurity ions diffuse (adhesive layer) The lead wiring WR1 and the land 16 are not arranged immediately below the solder resist layer SR1. Accordingly, the elution of metal (here, Cu) from the lead wiring WR1 and the land 16 to the solder resist layer SR1 can be suppressed or prevented, and Cu migration can be suppressed or prevented. Therefore, disconnection of the lead-out wiring WR1 and a short circuit between the lead-out wiring WR1 and the conductor pattern CP1 can be prevented, and the reliability of the semiconductor device can be improved.

  In the present embodiment, the lead-out wiring WR1 provided in the uppermost conductor layer M1 among the plurality of conductor layers M1 to M4 constituting the wiring board 2 is connected from the land 9 directly below the stiffener ring 6. It can extend to a region (but not a region directly below the adhesive layer 14). For this reason, the solder ball 5 can be disposed in a region immediately below the stiffener ring 6. That is, the lead-out wiring WR1 (and the land 16 connected thereto) extending from the land 9 to a region immediately below the stiffener ring 6 (but not directly below the adhesive layer 14), and the vias V1, V2, The land 9 can be electrically connected to the solder ball 5 located immediately below the stiffener ring 6 via V3 and the conductor layers M2, M3, and M4. For this reason, if this embodiment is applied when the plurality of solder balls 5 arranged on the lower surface 2b of the wiring board 2 include the solder balls 5 positioned immediately below the stiffener ring 6, the effect is great. In the present embodiment, the terminals 10 electrically connected to the lands 9 on the upper surface 2 a of the wiring board 2 and the solder balls 5 formed thereon are connected to the lower surface 2 b of the wiring board 2 immediately below the stiffener ring 6. By arranging in the region, it is possible to reduce the number of terminals and the size of the semiconductor device 1a.

  Further, the lead-out wiring WR1 and the land 16 are preferably separated from the region immediately below the adhesive layer 14 by 100 μm or more in the direction parallel to the upper surface 2a of the wiring board 2 for the same reason as in the first embodiment. is there.

(Embodiment 3)
FIG. 22 is a cross-sectional view (overall cross-sectional view, side cross-sectional view) of the semiconductor device 1b of the present embodiment, and FIG. 23 is a cross-sectional view of the main part of the semiconductor device 1b. This corresponds to FIG. FIG. 24 is a plan view of an essential part of the wiring board 2 used in the semiconductor device 1b of the present embodiment, and corresponds to FIG. 8 and FIG. Like FIG. 8 and FIG. 19, FIG. 24 shows a layout of the conductor layer M1 formed on the insulating layer 11 through the solder resist layer SR1, and FIG. 24 is a plan view. However, in order to make the drawing easy to see, the conductor layer M1 is hatched. Actually, the conductor layer M1 in the region shown in FIG. 24 is covered with the solder resist SR1. FIG. 25 is a plan view of the main part of the wiring board 2 in the same plane area as that in FIG. 24. In FIG. 25, the plane area in which the adhesive layer 14 is arranged is shown with bold hatching. This corresponds to FIG. 10 of the first embodiment and FIG. 20 of the second embodiment. However, in FIG. 25, the dotted line indicates the planar position of the lead-out wiring WR1 located under the adhesive layer 14, as in FIG. FIG. 26 is a partially enlarged plan view of FIG. 24. FIG. 26 also shows the layout of the conductor layer M1 formed on the insulating layer 11 through the solder resist layer SR1 as in FIG. In order to make the drawing easier to see, the conductor layer M1 (here, the lead-out wiring WR1, the land 16 and the conductor pattern CP1) is hatched. 24 and FIG. 26, the region in the range indicated by reference numeral RE3 is a region immediately below the adhesive layer 14, and the region in the range indicated by reference numeral RE4 is a region not immediately below the adhesive layer 14. is there.

  In the semiconductor device 1 of the first embodiment, the lead-out wiring WR1 is not arranged in the region immediately below the stiffener ring 6. On the other hand, in the semiconductor device 1b of the present embodiment, unlike the first embodiment, at least a part of the plurality of lead-out wirings WR1 provided on the upper surface 2a of the wiring substrate 2 is the stiffener ring 6. It extends (forms or is placed) directly under the area. In the semiconductor device 1a of the second embodiment, the adhesive layer 14 is not disposed immediately above the lead-out wiring WR1. On the other hand, in the semiconductor device 1b of the present embodiment, at least a part of the plurality of lead-out wirings WR1 provided on the upper surface 2a of the wiring board 2 is a region immediately below the stiffener ring 6 and the adhesive layer 14 It is also arranged in the area directly below. In order to solve the problem described in the first embodiment, the lead wires WR1 and WR2 are devised in the first embodiment, and the layout of the adhesive layer 14 is devised in the second embodiment. In the present embodiment, the interval between the lead-out wiring WR1 provided in the conductor layer M1 and the conductor pattern CP1 is devised.

  That is, in the present embodiment, the entire lower surface 6 b of the stiffener ring 6 is bonded to the upper surface 2 a of the wiring board 2 via the adhesive layer 14, and the region immediately below the stiffener ring 6 is directly below the adhesive layer 14. It corresponds to the area of. 24 and FIG. 25, the lead-out wiring WR1 provided in the conductor layer M1 extends to the region directly under the stiffener ring 6, that is, the region directly under the adhesive layer 14. Yes.

  However, in the semiconductor device 1b of the present embodiment, the spacing between the lead-out wiring WR1 provided in the conductor layer M1 and the conductor pattern CP1 is not the same in the entire region of the upper surface 2a of the wiring board 2. In addition, in the region immediately below the adhesive layer 14 (corresponding to the region RE3 in FIG. 24 and FIG. 26) and the region other than directly below the adhesive layer 14 (corresponding to the region RE4 in FIG. 24 and FIG. 26) The interval between WR1 and conductor pattern CP1 is changed. That is, as shown in FIGS. 24 and 26, the interval W1 between the lead-out wiring WR1 and the conductor pattern CP1 in the region immediately below the adhesive layer 14 (corresponding to the region RE3 in FIGS. 24 and 26) is: It is wider than the interval W2 between the lead-out wiring WR1 and the conductor pattern CP1 in a region other than immediately below the adhesive layer 14 (corresponding to the region RE4 in FIGS. 24 and 26) (that is, W1> W2).

  Since the other configuration of the semiconductor device 1b of the present embodiment is substantially the same as that of the semiconductor device 1 of the first embodiment, the description thereof is omitted here.

  In FIG. 27, unlike the present embodiment, the distance W3 between the lead-out wiring WR1 provided in the conductor layer M1 and the conductor pattern CP1 is the same in the entire area of the upper surface 2a of the wiring board 2. It is a principal part top view of a wiring board, and is equivalent to FIG. 26 of this Embodiment. In the case of FIG. 27, the space W3 between the lead-out wiring WR1 and the conductor pattern CP1 in the region immediately below the adhesive layer 14 (corresponding to the region RE3 in FIG. 27), and the region other than directly below the adhesive layer 14 ( The distance W3 between the lead-out wiring WR1 and the conductor pattern CP1 in the region RE4 in FIG. 27 is the same.

  As described above, when the impurity ions contained in the adhesive layer 14 diffuse into the solder resist layer SR1 in the severe high-temperature and high-humidity bias test, the lead-out wiring WR1 and the conductor pattern CP1 that are in contact with the solder resist layer SR1. The metal (Cu in this case) elutes to the solder resist layer SR1 side, and the lead-out wiring WR1 and the conductor pattern CP1 are connected via the eluted metal (Cu), which may cause a short circuit. In order to prevent this, it is effective to widen the interval between the lead-out wiring WR1 and the conductor pattern CP1. If the distance between the lead-out wiring WR1 and the conductor pattern CP1 is wide, even if metal (here, Cu) is eluted from the lead-out wiring WR1 and the conductor pattern CP1 to the solder resist layer SR1, the lead-out wiring WR1 Since it becomes difficult to be connected to the conductor pattern CP1 by the eluted metal, a short circuit between the lead-out wiring WR1 and the conductor pattern CP1 can be suppressed or prevented.

  On the other hand, when the interval between the lead-out wiring WR1 and the conductor pattern CP1 is increased, the effect of providing the conductor pattern CP1 to which the fixed potential is supplied around the lead-out wiring WR1 is reduced. That is, in order to improve the stability against noise of the signal passing through the lead-out wiring WR1, it is desirable that the distance between the lead-out wiring WR1 and the conductor pattern CP1 is small.

  However, when the distance W3 between the lead-out wiring WR1 and the conductor pattern CP1 is the same in the entire area of the upper surface 2a of the wiring board 2 as shown in FIG. 27, the space between the lead-out wiring WR1 and the conductor pattern CP1 If the interval W3 is increased in order to prevent the short circuit, the effect obtained by providing the conductor pattern CP1 is reduced, and the impedance also changes.

  On the other hand, in the present embodiment, as shown in FIGS. 24 and 26, the interval W1 between the lead-out wiring WR1 and the conductor pattern CP1 in the region immediately below the adhesive layer 14 is set as the adhesive layer 14. This is wider than the interval W2 between the lead-out wiring WR1 and the conductor pattern CP1 in the region other than immediately below (W1> W2). More preferably, the interval W1 between the lead-out wiring WR1 and the conductor pattern CP1 in the region immediately below the adhesive layer 14 is set between the lead-out wiring WR1 and the conductor pattern CP1 in the region other than directly below the adhesive layer 14. The interval W2 is 1.5 times or more (that is, W1> W2 × 1.5). For example, the interval W2 in the region other than directly below the adhesive layer 14 can be set to about 50 μm, and the interval W1 in the region immediately below the adhesive layer 14 can be set to about 80 μm or more.

  The land 16 can also be regarded as a part of the lead-out wiring WR1, and the distance between the land 16 and the conductor pattern CP1 in the region immediately below the adhesive layer 14 is approximately the same as the distance W1. be able to. Therefore, in the present embodiment, the distance between the land 16 and the conductor pattern CP1 in the region immediately below the adhesive layer 14 is such that the lead-out wiring WR1 and the conductor pattern CP1 in the region other than directly below the adhesive layer 14 are. The distance W2 is larger than the distance W2, more preferably 1.5 times or more the distance W2.

  Due to the diffusion of impurity ions contained in the adhesive layer 14 in the solder resist layer SR1 in the severe high-temperature, high-humidity bias test, the lead-out wiring WR1 and the conductor pattern CP1 can be short-circuited. In the region immediately below the adhesive layer 14 and in the region other than directly below the adhesive layer 14, the impurity diffusion of the adhesive layer 14 into the solder resist layer SR1 is small, so that no migration of Cu occurs, and a short circuit occurs almost. do not do.

  Therefore, as in the present embodiment, in the region immediately below the adhesive layer 14 where a short circuit between the lead-out wiring WR1 and the conductor pattern CP1 may occur, the space between the lead-out wiring WR1 and the conductor pattern CP1 By widening the interval W1, even if metal is eluted from the lead wiring WR1 and the conductor pattern CP1 to the solder resist layer SR1, the short circuit between the lead wiring WR1 and the conductor pattern CP1 can be suppressed or prevented. Can do. On the other hand, in a region other than immediately below the adhesive layer 14 where the short circuit hardly occurs, the interval W2 between the lead-out wiring WR1 and the conductor pattern CP1 is narrowed (narrower than the interval W1, more preferably 2/3 of the interval W1). By doing so, the stability of the signal passing through the lead-out wiring WR1 can be improved.

  Thus, in this embodiment, a short circuit between the lead-out wiring WR1 and the conductor pattern CP1 can be prevented, and the reliability of the semiconductor device can be improved. Further, the conductor pattern CP1 can increase the stability of the signal passing through the lead-out wiring WR1, and can improve the performance of the semiconductor device.

  In the present embodiment, the space between the lead-out wiring WR1 and the conductor pattern CP1 is wider in the region directly below the adhesive layer 14 than in the region other than directly below the adhesive layer 14. Furthermore, the width of the lead-out wiring WR1 can be made wider in the region immediately below the adhesive layer 14 than in the region other than directly below the adhesive layer 14, and this case is shown in FIG. FIG. 28 corresponds to FIG.

  In the present embodiment, as shown in FIG. 28, the width W4 of the lead-out wiring WR1 in the region immediately below the adhesive layer 14 (corresponding to the region RE3 in FIG. 27) is set to a value other than directly below the adhesive layer 14. It is more preferable that the width is larger than the width W5 of the lead-out wiring WR1 in the region (corresponding to the region RE4 in FIG. 27) (that is, W4> W5). More preferably, the width W4 of the lead-out wiring WR1 in the region immediately below the adhesive layer 14 is 1.5 times or more the width W5 of the lead-out wiring WR1 in the region other than directly below the adhesive layer 14 (that is, W4). > W5 × 1.5). For example, the width W5 in the region other than directly below the adhesive layer 14 can be set to about 20 μm, and the width W4 in the region directly below the adhesive layer 14 can be set to about 50 μm.

  The reason why the width of the lead-out wiring WR1 is made wider in the region immediately below the adhesive layer 14 than in the region other than directly below the adhesive layer 14 is as follows.

  As described above, when impurity ions contained in the adhesive layer 14 diffuse into the solder resist layer SR1 in a severe high-temperature and high-humidity bias test, a metal (here, from the lead-out wiring WR1 in contact with the solder resist layer SR1) In this case, Cu) elutes to the solder resist layer SR1 side and diffuses by bias. However, if the amount of elution is large, the lead-out wiring WR1 may be disconnected. In order to prevent this, it is effective to increase the width of the lead-out wiring WR1. If the width of the lead-out wiring WR1 is large, even if metal (Cu here) is eluted from the lead-out wiring WR1 to the solder resist layer SR1, the amount of metal in the lead-out wiring WR1 is large. Disconnection can be suppressed or prevented.

  On the other hand, if the width of the lead-out wiring WR1 is made too wide, it becomes difficult to route the lead-out wiring WR1 on the upper surface 2a of the wiring board 2, and the area of the wiring board 2 is difficult to be reduced. This is disadvantageous in terms of area.

  The lead wire WR1 may be disconnected due to the diffusion of impurity ions contained in the adhesive layer 14 into the solder resist layer SR1 in the severe high temperature and high humidity bias test. In the region immediately below the region, and the region other than the region directly below the adhesive layer 14, the impurities of the adhesive layer 14 are not diffused into the solder resist layer SR1, so that Cu migration does not occur and disconnection hardly occurs.

  For this reason, in the region immediately below the adhesive layer 14 where the disconnection of the lead-out wiring WR1 may occur as in the present embodiment, the width W4 of the lead-out wiring WR1 is increased, so that even from the lead-out wiring WR1. Even if the metal is eluted to the solder resist layer SR1, the disconnection of the lead-out wiring WR1 can be suppressed or prevented. On the other hand, in a region other than immediately below the adhesive layer 14 where disconnection hardly occurs, by narrowing the width W5 of the lead-out wiring WR1 (narrower than the width W4, more preferably 2/3 or less of the width W4) The lead wiring WR1 can be easily routed on the upper surface 2a of the wiring board 2, and the area of the wiring board 2 can be reduced (the area of the semiconductor device can be reduced).

  Thus, in this embodiment, disconnection of the lead-out wiring WR1 can be prevented, and the reliability of the semiconductor device can be improved. In addition, the semiconductor device can be reduced in size (smaller area).

  In the present embodiment, the lead-out wiring WR1 provided in the uppermost conductor layer M1 among the plurality of conductor layers M1 to M4 constituting the wiring board 2 is connected from the land 9 directly below the stiffener ring 6. It can be extended to a region (a region directly below the adhesive layer 14). For this reason, the solder ball 5 can be disposed in a region immediately below the stiffener ring 6. That is, the lead-out wiring WR1 (and the land 16 connected thereto) extending from the land 9 to the region immediately below the stiffener ring 6 (the region directly below the adhesive layer 14), the vias V1, V2, V3 and the conductor The lands 9 can be electrically connected to the solder balls 5 located immediately below the stiffener ring 6 via the layers M2, M3, and M4. For this reason, if this embodiment is applied when the plurality of solder balls 5 arranged on the lower surface 2b of the wiring board 2 include the solder balls 5 positioned immediately below the stiffener ring 6, the effect is great. In the present embodiment, the terminals 10 electrically connected to the lands 9 on the upper surface 2 a of the wiring board 2 and the solder balls 5 formed thereon are connected to the lower surface 2 b of the wiring board 2 immediately below the stiffener ring 6. By arranging in the region, it is possible to reduce the number of terminals and the size (reduction in area) of the semiconductor device 1b.

(Embodiment 4)
In the present embodiment, an example of a manufacturing process of the semiconductor devices 1, 1a, 1b of the first to third embodiments will be described. Since the semiconductor devices 1, 1a and 1b of the first to third embodiments can be manufactured by substantially the same process, an example of the manufacturing process of the semiconductor device 1 of the first embodiment will be representatively described here. To do.

  29 to 35 are cross-sectional views during the manufacturing process of the semiconductor device 1 of the first embodiment, and a cross section corresponding to FIG. 1 is shown.

  In the present embodiment, as an example, individual semiconductor devices are formed using a multi-piece wiring substrate (wiring substrate base) 21 formed by connecting a plurality of wiring substrates 2 (semiconductor device regions 22) in an array. The case where 1 is manufactured will be described. The wiring board 21 is a base body of the wiring board 2, and the semiconductor device is obtained by cutting the wiring board 21 in a cutting process to be described later and separating it into each semiconductor device region (substrate region, unit substrate region, device region) 22. This corresponds to one wiring board 2. The wiring substrate 21 has a configuration in which a plurality of semiconductor device regions 22 from which a single semiconductor device 1 is formed are arranged in a matrix (matrix). FIGS. A cross section of a region substantially corresponding to one semiconductor device region 22 is shown.

  First, the wiring board 21 and the semiconductor chip 3 are prepared. Here, as shown in FIG. 29, a wiring substrate 21 having a plurality of semiconductor device regions (unit substrate regions) 22, each of which is a unit substrate region from which the semiconductor device 1 is manufactured, includes an upper surface 21 a and an upper surface. A wiring board 21 having a lower surface 21b opposite to 21a, a plurality of lands 9 on the upper surface 21a of each semiconductor device region 22, and a plurality of terminals 10 on the lower surface 21b of each semiconductor device region 22 is prepared. Since the specific configuration of the wiring board 21 in each semiconductor device region 22 is the same as that of the wiring board 2, the description thereof is omitted here. The wiring board 21 is preferably manufactured by a build-up method so as to be compatible with fine pitch wiring, but other than that, a subtractive method, a printing method, a sheet lamination method, a semi-additive method, an additive method, or the like is used. Can be manufactured. Further, as described above, the semiconductor chip 3 has a plurality of bump electrodes 8 arranged on the surface 3 a of the semiconductor chip 3. The semiconductor substrate 3 is prepared after the wiring substrate 21 is prepared first, the wiring substrate 21 is prepared after the semiconductor chip 3 is prepared first, or the wiring substrate 21 and the semiconductor chip 3 are prepared simultaneously. May be.

  Thus, the wiring substrate 21 having the upper surface 21a on which the land 9 is arranged for each semiconductor device region 22 and the semiconductor chip 3 having the surface on which the plurality of bump electrodes 8 are arranged are prepared.

  After the wiring substrate 21 and the semiconductor chip 3 are prepared, a flip chip connection process is performed, and the semiconductor chip 3 is mounted on each semiconductor device region 22 of the upper surface 21a of the wiring substrate 21 as shown in FIG.

  In the flip chip connecting step of the semiconductor chip 3, the semiconductor chip 3 is face-down so that the back surface 3b side of the semiconductor chip 3 faces upward and the front surface 3a side of the semiconductor chip 3 faces downward (upper surface 21a side of the wiring substrate 21). Are arranged on the upper surface 21a of the wiring substrate 21 and aligned so that the plurality of bump electrodes 8 of the semiconductor chip 3 face the plurality of lands 9 on the upper surface 21a of the wiring substrate 21, respectively. When the bump electrode 8 is a gold bump, the semiconductor chip 3 is pressed against the wiring board 21 side, and the gold bump constituting the bump electrode 8 is pressed (pressed) against the land 9 of the wiring board 21. Crimp. At this time, the bump electrode 8 can be thermocompression bonded to the land 9 by applying pressure while heating. When the bump electrode 8 is a solder bump, the bump electrode 8 is connected to the land 9 (solder connection) by melting and resolidifying the solder bump constituting the bump electrode 8 by a solder reflow process (heat treatment). To do. As described above, the semiconductor chip 3 is mounted on the upper surface 21 a of the wiring substrate 21 via the plurality of bump electrodes 8, and the plurality of bump electrodes 8 of the semiconductor chip 3 are electrically connected to the plurality of lands 9 of the wiring substrate 21, respectively. Connecting.

  In addition, a protruding electrode is provided on each land 9 on the upper surface 21 a of the wiring substrate 21 before the semiconductor chip 3 is mounted, and the semiconductor chip is connected to the protruding electrode on the land 9 in the flip chip connecting step of the semiconductor chip 3. 3 bump electrodes 8 can be connected (joined).

  For example, bump electrodes 8 made of solder (solder bumps) are formed on the semiconductor chip 3, and solder protrusion electrodes (protrusion electrodes made of solder, solder bumps) are formed on each land 9 of the wiring board 21. In the flip chip connecting step, the semiconductor chip 3 is mounted so that the bump electrodes 8 of the semiconductor chip 3 and the solder protrusion electrodes on the lands 9 of the wiring substrate 21 face each other. Then, by performing the solder reflow process, the bump electrode 8 on the semiconductor chip 3 side can be connected (soldered) to the solder protrusion electrode on the wiring board 21 side. In this case, the bump electrode 8 of the semiconductor chip 3 and the solder protrusion electrode on the land 9 are integrated by the solder reflow process to form the bump electrode 8 after the semiconductor chip 3 is mounted, and each bump electrode 8 is electrically connected to each land 9. It will be connected to.

  Next, as shown in FIG. 31, a resin portion 4 as an underfill resin that fills between the semiconductor chip 3 and the wiring substrate 21 is formed. For example, a cured resin material is obtained by filling (injecting) a resin material (which may contain a filler) between the semiconductor chip 3 and the upper surface 21a of the wiring substrate 21 and curing the resin material by heating or the like. The resin part 4 which consists of can be formed. As another form, a resin material (filler is included in advance in a chip mounting scheduled area (an area where the semiconductor chip 3 is mounted later) of each semiconductor device area 22 on the upper surface 21a of the wiring board 21 before performing flip chip connection. After that, the bump electrode 8 of the semiconductor chip 3 is connected to the land 9 on the upper surface 21a of the wiring substrate 21 by flip chip connection, and then the resin material is cured to form the resin portion 4. You can also

  Next, as shown in FIG. 32, the stiffener ring 6 is mounted on each semiconductor device region 22 on the upper surface 21 a of the wiring substrate 21 via the adhesive layer 14. As the adhesive layer 14, a tape-type adhesive or a coating-type adhesive can be used. After mounting the stiffener ring 6, the stiffener ring 6 is bonded and fixed to the upper surface 21 a of the wiring substrate 21 via the adhesive layer 14 by performing a curing process (for example, a heating process) on the adhesive layer 14. When the tape type adhesive is used, when the stiffener ring 6 is mounted, the tape type adhesive has a certain degree of hardness. However, the tape type adhesive is once softened by heating and hardened after the adhesion is increased. As a result, the stiffener ring 6 is bonded to the upper surface 21a of the wiring substrate 21 via the tape-type adhesive (adhesive layer 14).

  As described above, the impurities in the adhesive in the high-temperature, high-humidity bias test under strict conditions as described above, regardless of whether a tape-type adhesive or a coating-type adhesive is used as the adhesive layer for bonding the stiffener ring to the wiring board. The above-mentioned problem that ions are diffused into the solder resist layer of the wiring board and Cu migration is promoted can occur. For this reason, the first to third embodiments are effective when applied to any one of the tape-type adhesive and the coating-type adhesive as the adhesive layer 14. However, if a tape-type adhesive is used as the adhesive layer 14, the uniformity of the thickness of the adhesive layer 14 can be increased, the adhesion is strong, and the flatness of the stiffener ring 6 can be increased. preferable. In the second embodiment, the layout of the adhesive layer 14 is devised. However, if a tape-type adhesive is used as the adhesive layer 14, the adhesive layer 14 can be easily arranged in a desired planar shape. In particular, in the second embodiment, it is preferable to use a tape-type adhesive as the adhesive layer 14.

  Next, as shown in FIG. 33, a common heat spreader 7 is mounted on the upper surface 6a of the stiffener ring 6 and the rear surface 3b of the semiconductor chip 3 via adhesive layers 15a and 15b. At this time, the adhesive layer 15 a is interposed between the lower surface 7 b of the heat spreader 7 and the upper surface 6 a of the stiffener ring 6, and the adhesive layer 15 b is interposed between the lower surface 7 b of the heat spreader 7 and the back surface 3 b of the semiconductor chip 3. . As the adhesive layer 15a and the adhesive layer 15b, either a tape type adhesive or a coating type adhesive can be used. The adhesive layer 15a and the adhesive layer 15b may use the same adhesive material or different adhesive materials, but if the same adhesive material is used, the manufacturing process of the semiconductor device can be simplified. After the heat spreader 7 is mounted, the adhesive layers 15a and 15b are cured so that the heat spreader 7 is bonded to the upper surface 6a of the stiffener ring 6 and the back surface 3b of the semiconductor chip 3 via the adhesive layers 15a and 15b. Fixed.

  Next, as shown in FIG. 34, the solder balls 5 are connected (bonded and formed) to the terminals 10 on the lower surface 21 b of the wiring board 21. In this solder ball 5 connecting step, for example, the lower surface 21b of the wiring board 21 is directed upward, and the solder balls 5 are arranged (mounted) on the plurality of terminals 10 of the respective semiconductor device regions 22 of the lower surface 21b of the wiring board 21. The solder ball 5 and the terminal 10 on the lower surface 21b of the wiring substrate 21 can be joined by temporarily fixing with a flux or the like and performing reflow processing (solder reflow processing, heat treatment) to melt the solder. Thereafter, a cleaning process may be performed as necessary to remove flux and the like attached to the surface of the solder ball 5. In this way, the solder balls 5 as external terminals (external connection terminals) of the semiconductor device 1 are joined (formed).

  In the present embodiment, the case where the solder ball 5 is joined as the external terminal of the semiconductor device 1 has been described. However, the present invention is not limited to this. For example, instead of the solder ball 5, the terminal 10 is formed by a printing method or the like. External terminals (bump electrodes, solder bumps) made of solder of the semiconductor device 1 can also be formed by supplying solder to the semiconductor device 1. In this case, solder is supplied to the plurality of terminals 10 in the respective semiconductor device regions 22 on the lower surface 21b of the wiring board 21, and then solder reflow processing is performed, so that external terminals (each made of solder are respectively formed on the plurality of terminals 10). Bump electrodes, solder bumps) can be formed. In addition, an external terminal (bump electrode) can be formed on each terminal 10 by performing a plating process or the like.

  In this manner, external connection terminals (here, solder balls 5) are formed on the plurality of terminals 10 in each semiconductor device region 22 on the lower surface 21b of the wiring board 21, respectively.

  Next, the wiring board 21 is cut. As a result, as shown in FIG. 35, the wiring substrate 21 is cut along the cutting regions between the respective semiconductor device regions 22, and each semiconductor device region 22 is divided into individual (separated) semiconductor devices 1. Into pieces (separated). That is, the wiring board 21 is cut and divided into each semiconductor device region 22, and the semiconductor device 1 is formed from each semiconductor device region 22. The wiring board 21 cut and separated (divided) into the respective semiconductor device regions 22 by this cutting step corresponds to the wiring board 2. Further, the upper surface 21 a of the wiring substrate 21 corresponds to the upper surface 2 a of the wiring substrate 2, and the lower surface 21 b of the wiring substrate 21 corresponds to the lower surface 2 b of the wiring substrate 2.

  In this way, the semiconductor device 1 is manufactured.

  As another form, after the multi-piece wiring board (wiring board base body) 21 is individually divided into the wiring board 2 first, the semiconductor chip 3 is flipped onto the wiring board 2 as described above. A step of chip connection can also be performed. Then, the semiconductor device 1 is manufactured by performing the above-described resin part 4 forming step, the above-described stiffener ring 6 mounting step, the above-described heat spreader 7 mounting step, and the above-described solder ball 5 connecting step.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a semiconductor device.

1, 1a, 1b Semiconductor device 2 Wiring board 2a Upper surface 2b Lower surface 3 Semiconductor chip 3a Front surface 3b Back surface 4 Resin part 5 Solder ball 6 Stiffener ring 6a Upper surface 6b Lower surface 7 Heat spreader 7b Lower surface 8 Bump electrode 9 Land 10 Terminals 11, 13 Insulating layer 12 Core layers 14, 15a, 15b Adhesive layers 16, 17, 18 Land 21 Wiring substrate 21a Upper surface 21b Lower surface 22 Semiconductor device region 102 Wiring substrate CP1, CP2 Conductor pattern DH Degas holes M1, M2, M3, M4 Conductor layers SR1, SR2 Solder resist layer V1, V2, V3 Via WR1, WR2 Lead-out wiring W1, W2, W3 Interval W4, W5 Width

Claims (2)

A wiring board having a first main surface on which a plurality of first terminals are arranged and a plurality of external terminals, and having a first back surface opposite to the first main surface;
A second main surface on which a plurality of projecting electrodes are arranged and a second back surface opposite to the second main surface, and the plurality of projecting electrodes are interposed on the first main surface of the wiring board. Mounted semiconductor chip,
A stiffener ring mounted on the outer periphery of the first main surface of the wiring board via an adhesive layer so as to surround the semiconductor chip;
Disposed on the first back surface of the wiring substrate, and the plurality of external terminals electrically connected to the plurality of first terminals,
A semiconductor device comprising:
The wiring board has a plurality of conductor layers, and the plurality of first terminals are formed by the first conductor layer of the uppermost layer of the plurality of conductor layers,
The plurality of protruding electrodes are electrically connected to the plurality of first terminals provided on the first main surface of the wiring board,
A plurality of first lead wirings formed on the first conductor layer and formed integrally with the plurality of first terminals , respectively , are formed on the first main surface of the wiring board;
The plurality of external terminals include a plurality of first external terminals that are formed of the second lowermost conductor layer of the plurality of conductor layers and are located immediately below the stiffener ring,
The plurality of first lead-out wirings are regions outside the region where the semiconductor chip is mounted, and extend to a region on the inner peripheral side from a region directly below the stiffener ring, A semiconductor device characterized in that it does not extend to a region of the main surface immediately below the stiffener ring. 2. The semiconductor according to claim 1, wherein the plurality of first lead-out wirings are signal wirings, and a power supply wiring pattern formed of the first conductor layer is further formed in a region immediately below the stiffener ring. apparatus.

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