JP2010245439A5 - - Google Patents

Claims (1)

A wiring board having a first main surface on which a plurality of first terminals are arranged and a first back surface opposite to the first main surface;
A second main surface on which a plurality of projecting electrodes are arranged and a second back surface opposite to the second main surface, and the plurality of projecting electrodes are interposed on the first main surface of the wiring board. Mounted semiconductor chip,
A stiffener ring mounted on the outer periphery of the first main surface of the wiring board via an adhesive layer so as to surround the semiconductor chip;
A plurality of external terminals disposed on the first back surface of the wiring board and electrically connected to the plurality of first terminals, respectively;
A semiconductor device comprising:
The wiring board has a plurality of conductor layers, and the plurality of first terminals are provided on the first conductor layer of the uppermost layer of the plurality of conductor layers,
The plurality of protruding electrodes are electrically connected to the plurality of first terminals provided on the first main surface of the wiring board,
A plurality of first lead wires provided on the first conductor layer and connected to the plurality of first terminals, respectively, are formed on the first main surface of the wiring board;
The plurality of external terminals include a plurality of first external terminals located immediately below the stiffener ring,
The plurality of first lead-out wirings extend to a region on the inner peripheral side than a region directly below the stiffener ring, and do not extend to a region directly below the stiffener ring on the first main surface. A semiconductor device characterized by the above.