JP5170531B2 - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 98
- 239000000758 substrate Substances 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 27
- 239000013078 crystal Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 5
- 230000037230 mobility Effects 0.000 claims 2
- 239000003990 capacitor Substances 0.000 claims 1
- 238000003860 storage Methods 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000009825 accumulation Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021471 metal-silicon alloy Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- -1 Si 3 N 4 Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Description
W1×L1+W2×L1=W3×L2を満足し、かつ
(gm1×W1/L1)+(gm2×W2/L1)=gm3×W3/L2
を満足するようにW1,W2,W3,L1,L2のうち残余の2つを定めることによって、
前記一導電型のトランジスタと前記他の導電型のトランジスタとを、チャンネル領域の面積を等しくなるようにすると共に、動作速度を互いに等しくなるようにしたものである。ここで、前記の第2の領域は、第1の半導体層の側面を傾斜面または垂直面とした部分に形成され、かつ両側面の一方のみを用いても、両方の上から一部または底部までを用いて形成されても良い。
W1+W2=W3×L2を満足し、かつ
gm1×W1+gm2×W2=gm3×W3
を満足するようにW1,W2,W3のうち残余の2つを定めるようにしたものである。
実施例1について図1を用いて説明する。図1(a)に本発明の第1の実施例による半導体装置の概略斜視図、図1(b)に図1(a)におけるA−A’線の断面図、図1(c)に図1(a)におけるB−B’線の断面図をそれぞれ示す。図1の実施例は、同一ディメンジョンで電流駆動能力がバランスするように設計したSOI型三次元構造CMOSデバイスであり、pチャンネルMOSトランジスタはホール移動度が大きくなる(110)面にのみ作製し、nチャンネルMOSトランジスタは電子移動度がやや劣る(110)面に加えて電子移動度の大きい側壁の(100)面をもゲートを構成するように作製したものである。すなわち、nチャンネル・トランジスタは三次元構造、pチャンネル・トランジスタはプレーナ構造にしたものである。
2 n型不純物領域
3a,3b 高濃度p型不純物領域
4a,4b 高濃度p型不純物領域
5 ゲート絶縁膜
6,7 ゲート電極
8 ゲート配線
9 出力配線
10,11 電源配線
12 支持基板
13 埋め込み酸化膜
14 SOI(Silicon on Insulator)層
15 ゲート絶縁膜
16 ゲート電極
17 ソース・ドレイン層(NMOSトランジスタ)
18 ソース・ドレイン層(PMOSトランジスタ)
19 ゲート配線
20 出力配線
21,22 電源配線
Claims (8)
- 異なる導電型のトランジスタを少なくとも一対有する回路を備えた半導体装置において、
SOI基板上の第1の半導体層とその表面の少なくとも一部を覆う第1のゲート絶縁層とを用いたnチャンネル・トランジスタと、
前記SOI基板上の第2の半導体層とその表面の少なくとも一部を覆う第2のゲート絶縁層を用いたpチャンネル・トランジスタとを有し、
前記第1の半導体層のチャネルを形成する第1の領域の表面が(110)面または(110)面から±10°以内の面を有すると共に、前記第1の半導体層の側面においてチャネルを形成する第2の領域の表面を(110)面から±10°以内の面とは異なりかつ(110)面から±10°以内の面よりも電子の移動度が大きい一つまたは複数の面を有し、
前記第2の半導体層のチャネルを形成する第3の領域の表面が(110)面または(110)面から±10°以内の面を有し、前記第1の領域の表面の面積と前記第2の領域の表面の面積との和が、前記第3の領域の表面の面積と等しくなるようにすると共に、前記nチャンネル・トランジスタと前記pチャンネル・トランジスタの動作速度が等しくなるように、前記第1の領域の表面の幅および長さ、前記第2の領域の表面の高さおよび長さ、ならびに前記第3の領域の表面の幅および長さを定めたことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、前記第2のゲート絶縁膜上に設けられる第2のゲート電極と前記第2の半導体層との仕事関数差により前記第2の半導体層に形成される空乏層の厚さが前記第2の半導体層の膜厚よりも大きくなるように前記第2のゲート電極の材料および前記第2の半導体層の不純物濃度が選択されていることを特徴とする半導体装置。
- 請求項1に記載の半導体装置において、前記第1のゲート絶縁膜上に設けられる第1のゲート電極と前記第1の半導体層との仕事関数差により前記第1の半導体層に形成される空乏層の厚さが前記第1の半導体層の膜厚よりも大きくなるように前記第1のゲート電極の材料および前記第1の半導体層の不純物濃度が選択されていることを特徴とする半導体装置。
- 異なる導電型のトランジスタを少なくとも一対有する回路を備えた半導体装置において、
SOI基板上に設けた第1の半導体層とその表面の少なくとも一部を覆う第1のゲート絶縁層とを用いて一導電型のトランジスタを形成するとともに、
前記SOI基板上に設けた第2の半導体層とその表面の少なくとも一部を覆う第2のゲート絶縁層を用いて他の導電型のトランジスタを形成し、
前記第1の半導体層のチャネルを形成する第1の領域の表面を第1の結晶面を有するようにするとともに前記第1の領域の表面と交差する面に設けられた前記第1の半導体層の側面においてチャネルを形成する第2の領域の表面を前記第1の結晶面とは異なりかつキャリアの移動度も異なる第2の結晶面を有するようにし、
前記第2の半導体層のチャネルを形成する第3の領域の表面を前記第1の結晶面を有するようにし、前記第1の領域の表面における相互コンダクタンスgmをgm1、前記第2の領域の表面における相互コンダクタンスgmをgm1より大きいgm2(即ち、gm2>gm1)とし、前記第3の領域の表面における相互コンダクタンスgmをgm1より大きいがgm2よりは小さいgm3(即ち、gm1<gm3<gm2)とし、前記第1の領域の表面の長さをL1、幅をW1、前記第2の領域の表面の長さをL1、幅をW2とし、前記第3の領域の表面の長さをL2、幅をW3とし、W1,W2,W3,L1,L2のうちどれか3つを所定の値としたときに、
W1×L1+W2×L1=W3×L2を満足し、かつ
(gm1×W1/L1)+(gm2×W2/L1)=gm3×W3/L2
を満足するようにW1,W2,W3,L1,L2のうち残余の2つを定めることによって、
前記一導電型のトランジスタと前記他の導電型のトランジスタとを、チャンネル領域の面積を互いに等しくかつ動作速度を互いに等しくなるようにしたことを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、前記L1と前記L2とを等しくすることによって、W1,W2,W3のうちどれか1つを所定の値として、
W1+W2=W3×L2を満足し、かつ
gm1×W1+gm2×W2=gm3×W3
を満足するようにW1,W2,W3のうち残余の2つを定めることを特徴とする半導体装置。 - 請求項4または5に記載の半導体装置において、前記第2の領域を前記第1の領域表面と垂直な面であって前記第1の領域表面の両側に延びる前記第1の半導体層の両側面の部分を用い、その領域の高さをHとして、前記W2を2Hとおくようにしたことを特徴とする半導体装置。
- 請求項6に記載の半導体装置において、前記一導電型のトランジスタと前記他の導電型のトランジスタの前記第1の結晶面を(110)面または(110)面から±10°以内の面としたことを特徴とする半導体装置。
- 請求項7に記載の半導体装置において、前記一導電型のトランジスタおよび前記他の導電型のトランジスタを、それぞれnチャンネル・トランジスタ、及び、pチャンネル・トランジスタとしたことを特徴とする半導体装置。
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JP2010067930A (ja) * | 2008-09-12 | 2010-03-25 | Toshiba Corp | 半導体装置およびその製造方法 |
CN102280454B (zh) * | 2011-08-22 | 2013-02-06 | 中国科学院半导体研究所 | 半导体晶体管结构及其制造方法 |
JP2013012768A (ja) * | 2012-09-05 | 2013-01-17 | Tohoku Univ | 半導体装置 |
KR101979637B1 (ko) | 2012-11-26 | 2019-08-28 | 삼성전자주식회사 | 반도체 소자 |
CN105308438A (zh) | 2013-06-10 | 2016-02-03 | 豪夫迈·罗氏有限公司 | 用于检测体液中分析物的方法和系统 |
US9224734B2 (en) * | 2013-09-13 | 2015-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS devices with reduced leakage and methods of forming the same |
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EP1959492A1 (en) | 2008-08-20 |
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WO2007063963A1 (ja) | 2007-06-07 |
JPWO2007063963A1 (ja) | 2009-05-07 |
US20090166739A1 (en) | 2009-07-02 |
US7800202B2 (en) | 2010-09-21 |
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