JP5153316B2 - 半導体パッケージ用放熱板およびそのめっき方法 - Google Patents

半導体パッケージ用放熱板およびそのめっき方法 Download PDF

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Publication number
JP5153316B2
JP5153316B2 JP2007330988A JP2007330988A JP5153316B2 JP 5153316 B2 JP5153316 B2 JP 5153316B2 JP 2007330988 A JP2007330988 A JP 2007330988A JP 2007330988 A JP2007330988 A JP 2007330988A JP 5153316 B2 JP5153316 B2 JP 5153316B2
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Prior art keywords
recess
heat sink
plating
semiconductor package
inner bottom
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JP2007330988A
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English (en)
Japanese (ja)
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JP2009152494A (ja
JP2009152494A5 (enExample
Inventor
修司 根来
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007330988A priority Critical patent/JP5153316B2/ja
Priority to KR1020080129029A priority patent/KR20090068140A/ko
Priority to CN2008101864797A priority patent/CN101465329B/zh
Priority to US12/339,725 priority patent/US20090183855A1/en
Publication of JP2009152494A publication Critical patent/JP2009152494A/ja
Publication of JP2009152494A5 publication Critical patent/JP2009152494A5/ja
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Publication of JP5153316B2 publication Critical patent/JP5153316B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
JP2007330988A 2007-12-21 2007-12-21 半導体パッケージ用放熱板およびそのめっき方法 Active JP5153316B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007330988A JP5153316B2 (ja) 2007-12-21 2007-12-21 半導体パッケージ用放熱板およびそのめっき方法
KR1020080129029A KR20090068140A (ko) 2007-12-21 2008-12-18 반도체 패키지용 방열판 및 그 도금 방법
CN2008101864797A CN101465329B (zh) 2007-12-21 2008-12-19 半导体封装用的散热板以及该散热板的电镀方法
US12/339,725 US20090183855A1 (en) 2007-12-21 2008-12-19 Heat radiating plate for semiconductor package and plating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007330988A JP5153316B2 (ja) 2007-12-21 2007-12-21 半導体パッケージ用放熱板およびそのめっき方法

Publications (3)

Publication Number Publication Date
JP2009152494A JP2009152494A (ja) 2009-07-09
JP2009152494A5 JP2009152494A5 (enExample) 2011-01-13
JP5153316B2 true JP5153316B2 (ja) 2013-02-27

Family

ID=40805811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007330988A Active JP5153316B2 (ja) 2007-12-21 2007-12-21 半導体パッケージ用放熱板およびそのめっき方法

Country Status (4)

Country Link
US (1) US20090183855A1 (enExample)
JP (1) JP5153316B2 (enExample)
KR (1) KR20090068140A (enExample)
CN (1) CN101465329B (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013528319A (ja) * 2010-05-21 2013-07-08 ノキア シーメンス ネットワークス オサケユキチュア ヒートシンクを部品に熱的に結合する方法及び装置
CN102299127B (zh) * 2011-07-13 2013-12-11 台达电子企业管理（上海）有限公司 用于封装元件的双向散热器及其组装方法
US10321554B2 (en) * 2015-10-05 2019-06-11 Mitsubishi Electric Corporation Electronic control unit
CN110648987B (zh) * 2019-10-11 2022-09-06 宁波施捷电子有限公司 一种界面导热材料层及其用途
CN114823573B (zh) * 2022-06-24 2022-09-09 威海市泓淋电力技术股份有限公司 一种散热型封装结构及其形成方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065699B2 (ja) * 1987-09-16 1994-01-19 日本電気株式会社 半導体装置
US5482898A (en) * 1993-04-12 1996-01-09 Amkor Electronics, Inc. Method for forming a semiconductor device having a thermal dissipator and electromagnetic shielding
US6461891B1 (en) * 1999-09-13 2002-10-08 Intel Corporation Method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
JP2001308215A (ja) * 2000-04-24 2001-11-02 Ngk Spark Plug Co Ltd 半導体装置
US6282096B1 (en) * 2000-04-28 2001-08-28 Siliconware Precision Industries Co., Ltd. Integration of heat conducting apparatus and chip carrier in IC package
JP4421118B2 (ja) * 2001-01-05 2010-02-24 富士通マイクロエレクトロニクス株式会社 半導体装置製造方法
JP3841768B2 (ja) * 2003-05-22 2006-11-01 新光電気工業株式会社 パッケージ部品及び半導体パッケージ
JP3809168B2 (ja) * 2004-02-03 2006-08-16 株式会社東芝 半導体モジュール
KR101007958B1 (ko) * 2006-02-24 2011-01-14 후지쯔 가부시끼가이샤 반도체 장치
JP5113346B2 (ja) * 2006-05-22 2013-01-09 日立電線株式会社 電子装置用基板およびその製造方法、ならびに電子装置およびその製造方法

Also Published As

Publication number Publication date
JP2009152494A (ja) 2009-07-09
CN101465329B (zh) 2013-05-22
CN101465329A (zh) 2009-06-24
US20090183855A1 (en) 2009-07-23
KR20090068140A (ko) 2009-06-25

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