JP5143769B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP5143769B2
JP5143769B2 JP2009041598A JP2009041598A JP5143769B2 JP 5143769 B2 JP5143769 B2 JP 5143769B2 JP 2009041598 A JP2009041598 A JP 2009041598A JP 2009041598 A JP2009041598 A JP 2009041598A JP 5143769 B2 JP5143769 B2 JP 5143769B2
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JP
Japan
Prior art keywords
manufacturing
conductive member
semiconductor device
gas
insulating film
Prior art date
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Expired - Fee Related
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JP2009041598A
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English (en)
Japanese (ja)
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JP2009218585A (ja
JP2009218585A5 (https=
Inventor
孝明 松岡
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009041598A 2008-03-12 2009-02-25 半導体装置およびその製造方法 Expired - Fee Related JP5143769B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6924408P 2008-03-12 2008-03-12
US61/069,244 2008-03-12

Publications (3)

Publication Number Publication Date
JP2009218585A JP2009218585A (ja) 2009-09-24
JP2009218585A5 JP2009218585A5 (https=) 2012-09-20
JP5143769B2 true JP5143769B2 (ja) 2013-02-13

Family

ID=41062143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009041598A Expired - Fee Related JP5143769B2 (ja) 2008-03-12 2009-02-25 半導体装置およびその製造方法

Country Status (5)

Country Link
US (1) US8278205B2 (https=)
JP (1) JP5143769B2 (https=)
KR (1) KR20090097827A (https=)
CN (1) CN101533799B (https=)
TW (1) TWI392056B (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120049239A (ko) * 2009-06-26 2012-05-16 도쿄엘렉트론가부시키가이샤 플라즈마 처리 방법
US9340880B2 (en) 2009-10-27 2016-05-17 Silcotek Corp. Semiconductor fabrication process
WO2012047945A2 (en) * 2010-10-05 2012-04-12 Silcotek Corp. Wear resistant coating, article, and method
US20120273948A1 (en) * 2011-04-27 2012-11-01 Nanya Technology Corporation Integrated circuit structure including a copper-aluminum interconnect and method for fabricating the same
US11292924B2 (en) 2014-04-08 2022-04-05 Silcotek Corp. Thermal chemical vapor deposition coated article and process
US10876206B2 (en) 2015-09-01 2020-12-29 Silcotek Corp. Thermal chemical vapor deposition coating
CN107887323B (zh) 2016-09-30 2020-06-05 中芯国际集成电路制造(北京)有限公司 互连结构及其制造方法
KR102616489B1 (ko) 2016-10-11 2023-12-20 삼성전자주식회사 반도체 장치 제조 방법
CN108231659B (zh) 2016-12-15 2020-07-07 中芯国际集成电路制造(北京)有限公司 互连结构及其制造方法
CN106783730B (zh) * 2016-12-28 2020-09-04 上海集成电路研发中心有限公司 一种形成空气隙/铜互连的方法
JP6441989B2 (ja) 2017-04-27 2018-12-19 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置、プログラムおよび記録媒体
US11161324B2 (en) 2017-09-13 2021-11-02 Silcotek Corp. Corrosion-resistant coated article and thermal chemical vapor deposition coating process
KR102866846B1 (ko) * 2019-05-20 2025-09-30 램 리써치 코포레이션 SiCxOy를 위한 핵생성 층으로서 SixNy
WO2020252306A1 (en) 2019-06-14 2020-12-17 Silcotek Corp. Nano-wire growth
US12473635B2 (en) 2020-06-03 2025-11-18 Silcotek Corp. Dielectric article
US11978668B2 (en) 2021-09-09 2024-05-07 Samsung Electronics Co., Ltd. Integrated circuit devices including a via and methods of forming the same
US20250273454A1 (en) * 2024-02-28 2025-08-28 Applied Materials, Inc. Microwave assisted passivation layer removal

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213343A (ja) * 1995-01-31 1996-08-20 Sony Corp 半導体装置およびその製造方法
EP1077479A1 (en) * 1999-08-17 2001-02-21 Applied Materials, Inc. Post-deposition treatment to enchance properties of Si-O-C low K film
JP2001185549A (ja) * 1999-12-24 2001-07-06 Toshiba Corp 半導体装置の製造方法
KR100762863B1 (ko) * 2000-06-30 2007-10-08 주식회사 하이닉스반도체 확산방지 티타늄-실리콘-질소 막을 이용한 구리금속배선방법
JP2002319618A (ja) * 2001-04-20 2002-10-31 Anelva Corp 配線用Ｃｕ膜の形成方法及び形成装置
JP2003045960A (ja) * 2001-08-01 2003-02-14 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP4293752B2 (ja) * 2002-02-28 2009-07-08 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2003347299A (ja) * 2002-05-24 2003-12-05 Renesas Technology Corp 半導体集積回路装置の製造方法
JP2004071956A (ja) 2002-08-08 2004-03-04 Toshiba Corp 半導体装置の製造方法
JP4454242B2 (ja) * 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
EP1691403A4 (en) * 2003-12-04 2009-04-15 Tokyo Electron Ltd METHOD FOR CLEANING THE CONDUCTIVE COATING SURFACE OF A SEMICONDUCTOR SUBSTRATE
US7229911B2 (en) * 2004-04-19 2007-06-12 Applied Materials, Inc. Adhesion improvement for low k dielectrics to conductive materials
US7193325B2 (en) * 2004-04-30 2007-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects
JP4473824B2 (ja) * 2005-01-21 2010-06-02 株式会社東芝 半導体装置の製造方法
US8211794B2 (en) * 2007-05-25 2012-07-03 Texas Instruments Incorporated Properties of metallic copper diffusion barriers through silicon surface treatments

Also Published As

Publication number Publication date
US8278205B2 (en) 2012-10-02
US20090230558A1 (en) 2009-09-17
CN101533799A (zh) 2009-09-16
CN101533799B (zh) 2011-10-05
TWI392056B (zh) 2013-04-01
TW200952119A (en) 2009-12-16
JP2009218585A (ja) 2009-09-24
KR20090097827A (ko) 2009-09-16

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