JP5137002B2 - メモリコントローラ - Google Patents

メモリコントローラ Download PDF

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Publication number
JP5137002B2
JP5137002B2 JP2007015096A JP2007015096A JP5137002B2 JP 5137002 B2 JP5137002 B2 JP 5137002B2 JP 2007015096 A JP2007015096 A JP 2007015096A JP 2007015096 A JP2007015096 A JP 2007015096A JP 5137002 B2 JP5137002 B2 JP 5137002B2
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JP
Japan
Prior art keywords
address
read
host system
data
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007015096A
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English (en)
Japanese (ja)
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JP2008181399A5 (enExample
JP2008181399A (ja
Inventor
崇彦 菅原
哲生 古都
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MegaChips Corp
Original Assignee
MegaChips Corp
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Filing date
Publication date
Application filed by MegaChips Corp filed Critical MegaChips Corp
Priority to JP2007015096A priority Critical patent/JP5137002B2/ja
Priority to US11/968,427 priority patent/US8375169B2/en
Publication of JP2008181399A publication Critical patent/JP2008181399A/ja
Publication of JP2008181399A5 publication Critical patent/JP2008181399A5/ja
Priority to US13/618,921 priority patent/US8725952B2/en
Application granted granted Critical
Publication of JP5137002B2 publication Critical patent/JP5137002B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/122Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7203Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
JP2007015096A 2007-01-25 2007-01-25 メモリコントローラ Expired - Fee Related JP5137002B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007015096A JP5137002B2 (ja) 2007-01-25 2007-01-25 メモリコントローラ
US11/968,427 US8375169B2 (en) 2007-01-25 2008-01-02 Memory controller
US13/618,921 US8725952B2 (en) 2007-01-25 2012-09-14 Memory controller for suppressing read disturb when data is repeatedly read out

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007015096A JP5137002B2 (ja) 2007-01-25 2007-01-25 メモリコントローラ

Publications (3)

Publication Number Publication Date
JP2008181399A JP2008181399A (ja) 2008-08-07
JP2008181399A5 JP2008181399A5 (enExample) 2010-05-13
JP5137002B2 true JP5137002B2 (ja) 2013-02-06

Family

ID=39669268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007015096A Expired - Fee Related JP5137002B2 (ja) 2007-01-25 2007-01-25 メモリコントローラ

Country Status (2)

Country Link
US (2) US8375169B2 (enExample)
JP (1) JP5137002B2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101050339B1 (ko) * 2008-08-19 2011-07-19 재단법인서울대학교산학협력재단 플래시 메모리 장치 및 데이터 읽기 방법
WO2010119784A1 (ja) 2009-04-14 2010-10-21 株式会社メガチップス メモリコントローラ、メモリ制御装置、メモリ装置、メモリ情報保護システム、メモリ制御装置の制御方法、およびメモリ装置の制御方法
JP5564197B2 (ja) 2009-04-23 2014-07-30 株式会社メガチップス メモリ制御装置、半導体メモリ装置、メモリシステム及びメモリ制御方法
US8688893B2 (en) * 2009-06-23 2014-04-01 Intel Mobile Communications GmbH Memory device and memory interface
JP5764392B2 (ja) 2011-06-13 2015-08-19 株式会社メガチップス メモリコントローラ
US10114750B2 (en) * 2012-01-23 2018-10-30 Qualcomm Incorporated Preventing the displacement of high temporal locality of reference data fill buffers
US9672887B2 (en) 2015-09-09 2017-06-06 Kabushiki Kaisha Toshiba Semiconductor memory capable of reading data without accessing memory cell
US20170075812A1 (en) * 2015-09-16 2017-03-16 Intel Corporation Technologies for managing a dynamic read cache of a solid state drive
KR20180019791A (ko) * 2016-08-16 2018-02-27 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
CN107403643B (zh) * 2017-07-17 2019-12-24 华中科技大学 一种通过重定向提高3d fg nand闪存可靠性的方法
GB2566729B (en) * 2017-09-22 2020-01-22 Imagination Tech Ltd Sorting memory address requests for parallel memory access
US10579517B2 (en) 2018-03-19 2020-03-03 Dell Products, Lp System and method for providing per channel frequency optimization in a double data rate memory system
WO2020000136A1 (en) 2018-06-25 2020-01-02 Alibaba Group Holding Limited System and method for managing resources of a storage device and quantifying the cost of i/o requests
US11061735B2 (en) 2019-01-02 2021-07-13 Alibaba Group Holding Limited System and method for offloading computation to storage nodes in distributed system
KR102301041B1 (ko) * 2019-07-04 2021-09-14 한국과학기술연구원 뉴로모픽 장치
US11617282B2 (en) 2019-10-01 2023-03-28 Alibaba Group Holding Limited System and method for reshaping power budget of cabinet to facilitate improved deployment density of servers
US11556277B2 (en) 2020-05-19 2023-01-17 Alibaba Group Holding Limited System and method for facilitating improved performance in ordering key-value storage with input/output stack simplification
US11507499B2 (en) 2020-05-19 2022-11-22 Alibaba Group Holding Limited System and method for facilitating mitigation of read/write amplification in data compression
US11487465B2 (en) 2020-12-11 2022-11-01 Alibaba Group Holding Limited Method and system for a local storage engine collaborating with a solid state drive controller
US11734115B2 (en) 2020-12-28 2023-08-22 Alibaba Group Holding Limited Method and system for facilitating write latency reduction in a queue depth of one scenario
US11726699B2 (en) 2021-03-30 2023-08-15 Alibaba Singapore Holding Private Limited Method and system for facilitating multi-stream sequential read performance improvement with reduced read amplification

Family Cites Families (26)

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JPS61253564A (ja) 1985-05-02 1986-11-11 Mitsubishi Electric Corp 記憶装置
JPS62130443A (ja) 1985-12-03 1987-06-12 Nec Corp メモリアクセス制御装置
JPS63276648A (ja) * 1987-05-08 1988-11-14 Mitsubishi Electric Corp デ−タ読出方式
JPH01100799A (ja) 1987-10-14 1989-04-19 Mitsubishi Electric Corp 読出し専用メモリ制御回路
JPH01134798A (ja) 1987-11-20 1989-05-26 Nec Corp メモリ制御装置
JPH0359741A (ja) 1989-07-28 1991-03-14 Mitsubishi Electric Corp キャッシュメモリ
JPH0594367A (ja) * 1991-10-02 1993-04-16 Shikoku Nippon Denki Software Kk バツフア記憶装置
JP2654603B2 (ja) * 1993-03-31 1997-09-17 日本電気株式会社 バッファ記憶装置におけるブロック置き換え制御方式
JPH0795307A (ja) 1993-09-21 1995-04-07 Omron Corp 自動通報装置の送信機
JP3130796B2 (ja) * 1996-06-26 2001-01-31 甲府日本電気株式会社 制御記憶装置
JPH10161939A (ja) * 1996-11-27 1998-06-19 Omron Corp メモリ制御装置
JP3474474B2 (ja) 1998-12-21 2003-12-08 モトローラ株式会社 半導体メモリ装置
US6715039B1 (en) * 2001-09-12 2004-03-30 Emc Corporation Cache slot promotion in a replacement queue cache using determinations of probabilities and costs
US20030206442A1 (en) * 2002-05-02 2003-11-06 Jerry Tang Flash memory bridiging device, method and application system
US6918020B2 (en) * 2002-08-30 2005-07-12 Intel Corporation Cache management
US6961821B2 (en) * 2002-10-16 2005-11-01 International Business Machines Corporation Reconfigurable cache controller for nonuniform memory access computer systems
US7117306B2 (en) * 2002-12-19 2006-10-03 Intel Corporation Mitigating access penalty of a semiconductor nonvolatile memory
TW200417850A (en) * 2003-03-06 2004-09-16 Macronix Int Co Ltd Device for reading sequential memory and method thereof
US7028156B1 (en) * 2003-07-01 2006-04-11 Veritas Operating Corporation Use of read data tracking and caching to recover from data corruption
KR100562906B1 (ko) * 2003-10-08 2006-03-21 삼성전자주식회사 시리얼 플래시 메모리에서의 xip를 위한 우선순위기반의 플래시 메모리 제어 장치 및 이를 이용한 메모리관리 방법, 이에 따른 플래시 메모리 칩
KR101085406B1 (ko) * 2004-02-16 2011-11-21 삼성전자주식회사 불 휘발성 메모리를 제어하기 위한 컨트롤러
US7177977B2 (en) * 2004-03-19 2007-02-13 Sandisk Corporation Operating non-volatile memory without read disturb limitations
US7337277B2 (en) * 2004-11-18 2008-02-26 International Business Machines Corporation Apparatus, system, and method for flushing cache data
JP2006209415A (ja) * 2005-01-27 2006-08-10 Matsushita Electric Ind Co Ltd マイクロコンピュータ
JP2006323739A (ja) * 2005-05-20 2006-11-30 Renesas Technology Corp メモリモジュール、メモリシステム、及び情報機器
US7711902B2 (en) * 2006-04-07 2010-05-04 Broadcom Corporation Area effective cache with pseudo associative memory

Also Published As

Publication number Publication date
JP2008181399A (ja) 2008-08-07
US8375169B2 (en) 2013-02-12
US20130013887A1 (en) 2013-01-10
US20080183982A1 (en) 2008-07-31
US8725952B2 (en) 2014-05-13

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