200417850 五、發明說明（1) 【發明領域】 本發明是有關於一種讀取記憶體之裝置及方法，且特 別是有關於一種讀取連續型唯讀記憶體（s e q u e n t i a 1 R 0 Μ ) 之裝置及方法。 發明背景】 度之記憶體，其接收位 用，以降低生產成本。 憶體（S e q u e n t i a 1 記憶體。連續型記憶體 待鎖定位址後，再讀出 一段比較長的時間，比 。除了鎖定位址的讀取 循序讀取。只要先鎖定 :read)的方式讀取其後 說，連續型記憶體内部 數器就可以每次於位址 不必每次皆執行鎖定 此連續型記憶體相當適 連續形態，以爆發式讀 於儲存程式，其速度慢 程式執行時會有許多跳 ，就必須跳到此副程式 連續型記憶體係為低成本高密 址之針腳與輸出資料之針腳係為共 連續型記憶體例如是連續型唯讀記 ROM)、NAND唯讀記憶體及NAND快閃 之傳統讀取方法係為先輸入位址， 資料。在鎖定位址及讀出資料需要 如是1 0 0 0 n s，因此其讀取速度不快 方法，連續型記憶體還利用計數器 位址，就可以用爆發式讀取（b u r s 1 之連續位址的資料。爆發式讀取是 有計數器，只要鎖定一位址後，計 增1而循序的輸出下個位址的資料 位址的動作，以加快讀取速度。因 合於儲存資料，因資料大部分係為 取可彌補其速度慢的缺點。 然而，如要將連續型記憶體用 的缺點就是一個必須克服鈞課題。 躍的指令，例如是執行一個副程式200417850 V. Description of the invention (1) [Field of the invention] The present invention relates to a device and method for reading memory, and in particular to a device for reading continuous read-only memory (sequentia 1 R 0 Μ) And methods. BACKGROUND OF THE INVENTION Memory is used to reduce the production cost. Memory (S equentia 1 memory. Continuous memory waits for a longer time after the address is locked, except that the address is read sequentially. As long as it is locked first: read) After that, the internal memory of the continuous memory can be locked at the address every time without having to execute the lock. This continuous memory is quite suitable for continuous mode. It reads the stored program in an explosive manner, and its speed is slow when the program runs. There are many jumps, it is necessary to jump to this subroutine. The continuous memory system is a low-cost high-density pin and the output data pins are co-continuous memory (such as continuous read-only memory), NAND read-only memory, and The traditional read method of NAND flash is to input the address and data first. If you need to lock the address and read the data, it needs to be 100 ns, so its reading speed is not fast. The continuous memory also uses the counter address, so you can use burst reading (burs 1 continuous address data). .Explosive reading is a counter. As long as one address is locked, it increments by 1 and sequentially outputs the data address of the next address to speed up the reading speed. Because it is suitable for storing data, most of the data This is to make up for the disadvantage of its slow speed. However, the disadvantage of using continuous memory is a problem that must be overcome. A jump command, for example, executes a subroutine.
TW0817PA(旺宏）.ptd 第4頁 200417850 五、發明說明（2) 的位址，這樣就必須重新鎖定位址以進行讀取。重新鎖定 位址再進行讀取係耗費相當多的時間，尤其程式執行中的 跳躍指令係頗頻繁，因此改進連續型記憶體之讀取速度係 為改進的目標。 發明 有 度之讀 根 法。首 錄於快 定之資 資料。 根 之裝置 讀取裝 元、記 並決定 登錄於 取位址 體，則 之資料 為 懂，下 目的及概 鑑於此， 取連續型 據本發明 先，接收 取記憶體 料；若否 據本發明 ，用以依 置包括快 憶體讀取 讀取位址 快取記憶 指定之資 記憶體言買 並輸出。 讓本發明 文特舉一 本發明的目的 記憶體之裝置 的目的，提出一種讀取連續 讀取位址。接 。若是，妁從 ，則從連續型 就是在提供 及方法。 提出一種讀取 從連續型記憶 取決定單元、 定單元用以接 快取記憶體。 取單元從快取 讀取位址未登 型記憶體讀出 特徵、和優點 並配合所附圖 述 的另一目的， 據一讀取位址 取記憶體、快 單元。快取決 是否已登錄於 體，則快取讀 料並輸出。若 取單元從連續 之上述目的、 較佳實施例， 著，決定讀取 快取記憶體輸 記憶體輸出言買 種改進讀取速 型記憶體的方 位址是否已登| 出讀取位址指 取位址指定之 連續型記憶體 體讀取資料。 快取讀取單 收讀取位址， 若讀取位址已 記憶體讀出讀 錄於快取記憶 讀取位址指定 能更明顯易 式，作詳細說TW0817PA (Wang Hong) .ptd Page 4 200417850 V. Description of the invention (2) The address must be re-locked for reading. Relocking the address and reading again takes a considerable amount of time, especially skip instructions during program execution are frequent, so improving the read speed of continuous memory is the goal of improvement. Invented a method of reading roots. First recorded in the quick information. The root device reads the device, records it, and decides to register it in the address body. The information is understood. The next purpose and general view of this is to take the continuous type according to the present invention. First, receive the memory material; if not, according to the present invention It is used to buy and output according to the specified memory words including cache memory read and read address cache memory. Let the present invention specifically mention the object of the present invention, the memory device, and propose a continuous read address. Then. If yes, follow from, then the continuous type is providing and method. This paper proposes a fetching decision unit and continuous unit from the continuous memory to access the cache memory. The fetch unit reads the features and advantages from the cache read address unregistered type memory and cooperates with another purpose described in the attached drawings to fetch the memory and the fast unit according to a read address. Cache depends on whether it is registered in the body, then the data will be cached and output. If the fetching unit continues from the above-mentioned purpose, the preferred embodiment, decide whether to read the cache memory, input the memory output, and buy an improved read-speed memory. The location address has been registered. Read data from the continuous memory specified by the address. Cache read list Receives the read address. If the read address has been read out from the memory, it is read into the cache memory. The read address designation can be more obvious and easier.
TW0817PM 旺宏）.ptd 第5頁 200417850 五、發明說明（3) . 明如下。 【較佳實施例】 本發明的精神在於利用快取記憶體加速連續型記憶體 的讀取速度。請參照第1圖，其繪示依照本發明一較佳實 施例的一種讀取連續型記憶體之方法的流程圖。本方法用 於一處理系統，包括一中央處理單元及一連續型記憶體。 處理系統還可能包括其他種類的記憶體，如動態隨機存取 記憶體（DRAM)、EEPROM等。連續型記憶體從中央處理單元 接收到一位址後，首先判斷此位址是否屬於此連續型記憶0 體，如步驟1 1 0所示：若否，表示此位址係屬於其他記憶 體，則結束本方法；若此你址屬於此連續型記憶體，則決 定此位址之内容是否已經存於快取記憶體（cache memory)，如步驟12 0所示。決定此位址之内容是否已經存 於快取記憶體的方法係比較此位址與快取記憶體的標記位 址（T A G a d d r e s s )。若有任一標記位址與此位址符合，表 示此位址所欲讀取的資料已存於快取記憶體，所以可以直 接從快取記憶體輸出資料，如步驟1 3 0所示。若沒有標記 位址與此位址符合，則必須從連續型記憶體讀取資料，如 步驟1 4 0所示，然後更新快取記憶體，如步驟1 5 0，以加快^ 下次的讀取。快取記憶體係可為直接映射式（d i r e c t mapp e d )或為集合關連式(set associative)0 第2圖繪示為步驟1 4 0之從連續型記憶體讀取資料之流 程圖。首先，決定此位址是否與上次讀取之位址屬於同一TW0817PM Wanghong) .ptd Page 5 200417850 V. Description of the Invention (3) The description is as follows. [Preferred Embodiment] The spirit of the present invention is to use the cache memory to accelerate the reading speed of the continuous memory. Please refer to FIG. 1, which shows a flowchart of a method for reading continuous memory according to a preferred embodiment of the present invention. The method is used in a processing system, including a central processing unit and a continuous memory. The processing system may also include other types of memory, such as dynamic random access memory (DRAM), EEPROM, and so on. After the contiguous memory receives an address from the central processing unit, it first determines whether the address belongs to the contiguous memory 0, as shown in step 1 10: if not, it indicates that the address belongs to other memory, Then the method ends; if your address belongs to the continuous memory, it is determined whether the content of this address is already stored in the cache memory, as shown in step 120. The method of determining whether the content of this address is already in the cache is to compare this address with the tag address of the cache (T A G a d d r e s s). If any of the marked addresses matches this address, it means that the data to be read at this address has been stored in the cache memory, so the data can be directly output from the cache memory, as shown in step 130. If no tagged address matches this address, you must read the data from the continuous memory, as shown in step 1 40, and then update the cache memory, as in step 1 50, to speed up the next reading ^ take. The cache memory system can be a direct mapping (d i r e c t mapp e d) or a set associative 0. Figure 2 shows the flow chart of reading data from the continuous memory in step 1 40. First, determine if this address is the same as the last read address
TW0817PA(旺宏）.ptd 第6頁 200417850 五、發明說明（4) 頁（page hi t)，如步驟21 3所示。若非為同一頁，則開始 鎖定位址之週期（address latch cycle)，如步驟2 4 0所 示。一段時間後，如約1 0 0 0 n s，即可輸出資料，如步驟 2 5 0所示。若為同一頁，則再決定此位址與上次讀取的位 址之差距是否小於等於7，如步驟2 2 0所示。若是，依上次 讀取的位址循序讀到此位址之資料而輸出，如步驟2 3 0所 示；若否，則執行步驟2 4 0。在步驟2 3 0中，循序讀取資料 的方法係只利用記憶體内部之計數器從上次位址開始計數 到此次位址才輸出資料。鎖定位址的方式需等1 0 0 0 n s後才 能開始讀取，每次讀取需2 0 0ns，因此在位址差距在7之内 使用循序讀取的方式會比鎖定位址的方式來的快，超過7 的話就使用傳統的鎖定位址的方式讀取。 第3圖繪示為依照本發涧之一種讀取連續型記憶體之 裝置3 0 0，用以依據一讀取位址A從連續型記憶體1 0 0讀取 資料D。讀取裝置3 0 0包括快取記憶體3 1 0、快取決定單元 3 2 0、快取讀取單元3 3 0、記憶體讀取單元3 4 0。快取決定 單元3 2 0用以接收讀取位址A，並決定讀取位址A是否已登 錄於快取記憶體3 1 0。若讀取位址A已登錄於快取記憶體 3 1 0，則快取讀取單元3 3 0從快取記憶體3 1 0讀出讀取位址A 指定之資料D並輸出。若讀取位址A未登錄於快取記憶體 3 1 0，則記憶體讀取單元3 4 0從連續型記憶體1 0 0讀出讀取 位址A指定之資料D並輸出- 讀取裝置30 0更可包括一快取更新單元（未繪於圖式 )，用以將記憶體讀取單元3 4 0輸出之該資料更新於該快 assn· TW0817PA(旺宏）.ptd 第7頁 200417850 五、發明說明（5) 取記憶體。記憶體讀取單元3 4 0包括頁次決定單元、差距 決定單元、與循序讀取單元（未繪於圖式）。頁次決定單 元用以決定讀取位址A與上次讀取之一前次位址是否屬於 同一頁。若讀取位址A與前次位址屬於同一頁，則差距決 定單元再決定讀取位址A與前次位址之差距是否小於一預 設值，例如為7。若讀取位址A與前次位址之差距小於預設 值，則循序讀取單元即循序地從前次位址開始讀取連續型 記憶體1 0 0，依序讀到讀取位址A後輸出讀取位址指定之資 料D。若讀取位址A與前次位址不屬於同頁或其差距大於預 設值，則鎖定單元開始鎖定（1 atch)讀取位址A。然後，輸; 出單元依據鎖定之讀取位址A從連續型記憶體1 0 0輸出該資 料D。 綜上所述，本發明利用快取記憶體以增進連續型記憶 體的讀取速度，並且還利3循序讀取的方法以增進直接讀 取連續型記憶體的速度。 :發明效果】 本發明上述實施例所揭露之讀取連續型記憶體的裝置 及方法利用快取記憶體及循序讀取的方法以增進連續型記 憶體的讀取速度。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍内，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為TW0817PA (Wang Hong) .ptd Page 6 200417850 V. Description of the invention (4) Page (page hi t), as shown in step 21 3. If it is not the same page, the address latch cycle is started, as shown in step 2 40. After a period of time, such as about 100 0 n s, the data can be output, as shown in step 2 50. If it is the same page, then decide whether the difference between this address and the last read address is less than or equal to 7, as shown in step 2 2 0. If it is, the data is sequentially output according to the last read address, as shown in step 2 30; if not, go to step 2 40. In step 230, the method of sequentially reading data is to output data only by counting from the last address in the internal counter of the memory to the current address. The method of locking the address needs to wait for 1 0 0 0 ns before starting to read, and each reading requires 2 0 0 ns. Therefore, using the sequential reading method within the address gap within 7 will be more effective than the method of locking the address. It's fast. If it is more than 7, it will use the traditional way to read the address. FIG. 3 shows a device 300 for reading continuous memory according to the present invention, which is used to read data D from the continuous memory 100 according to a reading address A. The reading device 3 0 0 includes a cache memory 3 1 0, a cache determination unit 3 2 0, a cache reading unit 3 3 0, and a memory reading unit 3 4 0. The cache determination unit 3 2 0 is used to receive the read address A, and determines whether the read address A has been registered in the cache memory 3 1 0. If the read address A is registered in the cache memory 3 1 0, the cache read unit 3 3 0 reads out the data D specified by the read address A and outputs it. If the read address A is not registered in the cache memory 3 1 0, the memory read unit 3 4 0 reads the data D specified by the read address A from the continuous memory 1 0 0 and outputs-read The device 300 may further include a cache update unit (not shown in the figure) for updating the data output from the memory reading unit 3 4 0 to the fast assn · TW0817PA (Wanghong) .ptd page 7 200417850 V. Description of the invention (5) Take the memory. The memory reading unit 340 includes a page determination unit, a gap determination unit, and a sequential reading unit (not shown in the figure). The page determination unit is used to determine whether the read address A and the previous address of the last read belong to the same page. If the read address A and the previous address belong to the same page, the gap determination unit determines whether the difference between the read address A and the previous address is less than a preset value, such as 7. If the difference between the read address A and the previous address is less than the preset value, the sequential reading unit sequentially reads the continuous memory 1 0 0 from the previous address, and sequentially reads the read address A Then output the data D specified by the read address. If the read address A and the previous address do not belong to the same page or the gap is greater than the preset value, the lock unit starts to lock (1 atch) to read the address A. Then, the output unit outputs the data D from the continuous memory 100 according to the locked read address A. In summary, the present invention utilizes a cache memory to improve the read speed of the continuous memory, and also uses a sequential read method to increase the speed of directly reading the continuous memory. : Effect of the Invention] The apparatus and method for reading continuous memory disclosed in the above embodiments of the present invention utilize a cache memory and a sequential reading method to improve the reading speed of the continuous memory. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be defined as
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TW0817PA(旺宏）.ptd 第9頁 200417850 圖式簡單說明 第1圖繪示依照本發明一較佳實施例的一種讀取連續型 記憶體之方法的流程圖。 第2圖繪示為從連續型記憶體讀取資料之流程圖。 第3圖繪示為依照本發明之一種讀取連續型記憶體之 裝置。 【圖式標號說明】 100 連 續 型 記 憶 體 300 讀 取 連 續 型 記 憶體之裝置 310 快 取 記 憶 體 320 快 取 決 定 單 元 330 快 取 讀 取 單 元 340 記 憶 體 讀 取 單 元TW0817PA (Wang Hong) .ptd Page 9 200417850 Brief Description of Drawings Figure 1 shows a flowchart of a method for reading continuous memory according to a preferred embodiment of the present invention. FIG. 2 shows a flowchart for reading data from the continuous memory. FIG. 3 shows a device for reading continuous memory according to the present invention. [Illustration of drawing labels] 100 continuous memory units 300 reading continuous memory units 310 cache memory units 320 cache decision units 330 cache memory units 340 memory memory units
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