JP5117451B2 - スイッチトキャパシタ回路、およびアナログデジタル変換器 - Google Patents
スイッチトキャパシタ回路、およびアナログデジタル変換器 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/0607—Offset or drift compensation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
- H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
- H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
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Description
図4は、実施の形態1に係るスイッチトキャパシタ回路300のオートゼロ状態の様子を示す図である。この状態では、正側の入力容量(Cs1p、Cs2p、・・・)および正側の調整容量Cxpのすべてに、正側の入力アナログ信号Vinpが入力され、負側の入力容量(Cs1m、Cs2m、・・・)および負側の調整容量Cxmのすべてに、負側の入力アナログ信号Vinmが入力される。また、正側の追加調整容量Cexpに正側の第1追加調整電圧Vexp1が入力され、負側の追加調整容量Cexmに負側の第1追加調整電圧Vexm1が入力される。
Qm=Cs*16*(Vinm−Vazm)+Cf*(VRB2−Vazm)+Cexm*(Vexm1−Vazm) ・・・(式2)
Vazpは、オートゼロ状態における、正側の第1インバータINV1pの入力端子電圧および出力端子電圧を示す。換言すれば、正側の第1インバータINV1pのオフセット成分が加味された、正側の第1インバータINV1pの出力反転電圧といえる。
Vazmは、オートゼロ状態における、負側の第1インバータINV1mの入力端子電圧および出力端子電圧を示す。換言すれば、負側の第1インバータINV1mのオフセット成分が加味された、負側の第1インバータINV1mの出力反転電圧といえる。
Qp=Cs*{n*VRT+(15−n)*VRB+Vxp−16*Vazp}+Cf*(Voutp−Vazp)+Cexp*(Vexp2−Vazp) ・・・(式3)
Qm=Cs*{n*VRB+(15−n)*VRT+Vxm−16*Vazm}+Cf*(Voutm−Vazm)+Cexm*(Vexm2−Vazm) ・・・(式4)
nは、正側の入力容量Cspにおいて、高電位側基準電圧VRTが入力される入力容量Cspの数を示す。
Voup−Voutm=Cs/Cf*{16*(Vinp−Vinm)+VRT*(15−2n)+VRB*(2n−15)+(Vxp−Vxm)}+Cexp/Cf*(Vexp1−Vexp2)−Cexm/Cf*(Vexm1−Vexm2) ・・・(式5)
Qm=Cs*16*(Vinm−Vazm)+Cf*(VRB2−Vazm)+Cexm*(Vexm1+Im*Tm−Vazm) ・・・(式7)
Ipは、正側の定電流源CISpに流れる電流を示し、Tpは、正側の定電流源スイッチMsipがオンしている時間を示す。
Imは、負側の定電流源CISmに流れる電流を示し、Tmは、負側の定電流源スイッチMsimがオンしている時間を示す。
Qp=Cs*{n*VRT+(15−n)*VRB+Vxp−16*Vazp}+Cf*(Voutp−Vazp)+Cexp*(Vexp1−Vazp) ・・・(式8)
Qm=Cs*{n*VRB+(15−n)*VRT+Vxm−16*Vazm}+Cf*(Voutm−Vazm)+Cexm*(Vexm1−Vazm) ・・・(式9)
nは、正側の入力容量Cspにおいて、高電位側基準電圧VRTが入力される入力容量Cspの数を示す。
Voup−Voutm=4*{(Vinp−Vinm)−(2n−15)/8*(VRT−VRB)+(Vxp−Vxm)/16}−Cexp*Ip*Tp+Cexm*Im*Tm ・・・(式10)
Qm=Cs*16*(Vinm−Vazm)+Cf*(VRB2−Vazm)+Cx2m*(Vexm−Im*Tm−Vazm) ・・・(式12)
Ipは、正側の定電流源CISpに流れる電流を示し、Tpは、正側の定電流源スイッチMsipがオンしている時間を示す。
Imは、負側の定電流源CISmに流れる電流を示し、Tmは、負側の定電流源スイッチMsimがオンしている時間を示す。
Claims (4)
- 複数の入力信号を受け、それらを合成して一つの出力信号を生成して出力する容量アレイ回路と、
前記容量アレイ回路の出力信号を受けるコンパレータと、
所定の固定電圧源と当該スイッチトキャパシタ回路の出力端子との間に設けられ、前記コンパレータの出力信号が変化するまで、電流を当該出力端子に供給する電流源と、を備え、
前記容量アレイ回路は、
前記複数の入力信号をそれぞれ並列に受ける複数の入力容量と、
前記コンパレータの遅延に起因するオフセット成分を補償するための電荷を蓄える調整容量と、を含み、
前記複数の入力容量および前記調整容量のそれぞれの出力端子が一つに結合されていることを特徴とするスイッチトキャパシタ回路。 - 前記調整容量の入力端子に接続された定電流源と、
所定の固定電圧源と前記定電流源との間に設けられたスイッチと、をさらに備え、
前記コンパレータのオートゼロ期間に、前記複数の入力容量の入力端子に前記入力信号が入力され、かつ前記調整容量の入力端子に、調整電圧と前記定電流源から供給される電流にもとづく電圧とが順に入力され、
前記コンパレータの増幅期間に、前記入力容量の入力端子に所定のリファレンス電圧が入力され、かつ前記調整容量の入力端子に前記調整電圧が入力され、
前記コンパレータのオートゼロ期間の一部の期間に、前記スイッチが前記コンパレータの遅延に対応する時間、オンすることにより、前記定電流源から前記調整容量の入力端子に電流が供給されることを特徴とする請求項1に記載のスイッチトキャパシタ回路。 - 前記コンパレータの遅延時間を推測するためのダミー遅延回路を含む遅延量検出回路をさらに備え、
前記遅延量検出回路は、前記ダミー遅延回路により推測された遅延時間にもとづいて、前記スイッチがオンする時間を決定することを特徴とする請求項2に記載のスイッチトキャパシタ回路。 - 入力アナログ信号を、上位ビットから下位ビットに向けて複数回の変換処理により、デジタル信号に変換するアナログデジタル変換器であって、
第1アナログ信号を所定ビット数のデジタル信号に変換するサブAD変換回路と、
前記サブAD変換回路により変換されたデジタル信号を第2アナログ信号に変換するDA変換回路と、
前記第1アナログ信号または所定の増幅率で増幅された後の前記第1アナログ信号から、前記第2アナログ信号を減算する減算回路と、
前記減算回路により減算された、前記第1アナログ信号と前記第2アナログ信号との差分信号を増幅し、つぎの変換処理の対象とすべきアナログ残差信号を生成する増幅回路と、を備え、
前記DA変換回路、前記減算回路、および前記増幅回路が、請求項1から3のいずれかに記載のスイッチトキャパシタ回路により構成されることを特徴とするアナログデジタル変換器。
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US12/825,744 US8223058B2 (en) | 2009-06-30 | 2010-06-29 | Switched-capacitor circuit having a capacitor array circuit, and analog-to-digital converter using said switched-capacitor circuit |
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CN103069719B (zh) * | 2010-07-08 | 2016-10-05 | 密克罗奇普技术公司 | 使用斩波器电压参考的用于切换式电容器σ-δ调制器的二阶段增益校准和缩放方案 |
US9069364B2 (en) * | 2012-03-23 | 2015-06-30 | Fairchild Semiconductor Corporation | Enhanced on-time generator |
US9899846B2 (en) | 2012-08-30 | 2018-02-20 | Carver Scientific, Inc. | Entropic energy transfer methods and circuits |
JP2016225840A (ja) | 2015-05-29 | 2016-12-28 | 株式会社東芝 | 増幅回路、ad変換器、無線通信装置、及びセンサシステム |
JP2016225951A (ja) * | 2015-06-03 | 2016-12-28 | 株式会社東芝 | 増幅回路及びアナログ/デジタル変換回路 |
JP2017055241A (ja) * | 2015-09-09 | 2017-03-16 | 株式会社東芝 | 増幅器、電気回路、及びイメージセンサ |
JP2017168930A (ja) | 2016-03-14 | 2017-09-21 | 株式会社東芝 | スイッチトキャパシタ回路 |
EP3549232A1 (en) | 2016-12-02 | 2019-10-09 | Carver Scientific, Inc. | Memory device and capacitive energy storage device |
CN109639282B (zh) * | 2018-10-25 | 2021-08-24 | 西安电子科技大学 | 一种单端输入的低功耗同步寄存器型逐次逼近adc |
EP3829058A1 (en) * | 2019-11-26 | 2021-06-02 | ams International AG | Switched-capacitor amplifier and pipelined analog-to-digital converter comprising the same |
US11658678B2 (en) * | 2020-08-10 | 2023-05-23 | Analog Devices, Inc. | System and method to enhance noise performance in a delta sigma converter |
US11177821B1 (en) * | 2020-08-11 | 2021-11-16 | Analog Devices, Inc. | Analog-to-digital converter with auto-zeroing residue amplification circuit |
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US6914550B2 (en) * | 2003-10-09 | 2005-07-05 | Texas Instruments Incorporated | Differential pipelined analog to digital converter with successive approximation register subconverter stages using thermometer coding |
JP4382040B2 (ja) * | 2003-10-21 | 2009-12-09 | 富士通マイクロエレクトロニクス株式会社 | D/a変換回路 |
US6870495B1 (en) * | 2004-02-18 | 2005-03-22 | Micron Technology, Inc. | Double throughput analog to digital converter |
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JP4836574B2 (ja) * | 2005-12-28 | 2011-12-14 | オンセミコンダクター・トレーディング・リミテッド | アナログデジタル変換器およびしきい値補正方法 |
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JP4480744B2 (ja) * | 2007-07-31 | 2010-06-16 | 三洋電機株式会社 | アナログデジタル変換器 |
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