JP5102214B2 - 電荷補償構造を有するパワー半導体素子 - Google Patents
電荷補償構造を有するパワー半導体素子 Download PDFInfo
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- JP5102214B2 JP5102214B2 JP2008536924A JP2008536924A JP5102214B2 JP 5102214 B2 JP5102214 B2 JP 5102214B2 JP 2008536924 A JP2008536924 A JP 2008536924A JP 2008536924 A JP2008536924 A JP 2008536924A JP 5102214 B2 JP5102214 B2 JP 5102214B2
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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Description
2 パワー半導体素子(第2実施形態)
3 電荷補償構造
4 半導体基材
5 ドリフト経路
6 ソース電極
7 ドレイン電極
8 ゲート電極
9 ドリフト領域、第1ドリフト領域型
10 ドリフト領域、第2ドリフト領域型
11 電荷補償領域
12 単結晶基板
13 トレンチ構造物
14 トレンチ構造物の壁
15 トレンチ構造物の壁
16 トレンチ構造物の壁上の相補伝導層
17 中濃度にドープされたエピタキシャル層
18 半導体基材の上面
19 基板の上面
20 下地エピタキシャル層
21 下地エピタキシャル層の上面
22 充填された単結晶半導体材料
23 拡散阻害層
24 エッジ構造物
25 エッジトレンチ
26 エッジ補償領域
27 パワー半導体素子のエッジ
28 エッジ輪郭
29 エッジパッシベーション層
30 トレンチ構造物の底部
31 半導体基材の背面
32 パターン形成された補助層
33 終点制御層
34 メサの上面
35 メサ
36 トレンチ構造物の壁上の高濃度にドープされた単結晶のエピタキシャル層
37 平らにしているフォトレジスト層
38 エッジ領域
39 p伝導型ボディー領域
40 破線
D ドレイン電極
G ゲート電極
S ソース電極
h 上記メサの高さ
t トレンチ深さ
W 上記エピタキシャル層の層厚
Claims (22)
- 電荷補償構造を有するパワー半導体素子であって、パワー半導体素子(3)は、半導体基材(4)内において、2つの電極(6、7)間にドリフト経路(5)を有し、上記ドリフト経路(5)は、上記ドリフト経路(5)内の上記電極(6、7)間に電流経路を提供する第1伝導型(n)ドリフト領域(9、10)、及び上記ドリフト経路(5)の上記電流経路を制限する相補伝導型(p)電荷補償領域(11)を有し、上記ドリフト領域(9、10)は、交互に配置された、2つの第1伝導型(n)ドリフト領域を有し、第1ドリフト領域(9)は、単結晶基板(12)上における単結晶半導体材料を有し、かつ第2ドリフト領域(10)は、相補的にドープされた壁(14、15)を有する構造物(13)内における単結晶半導体材料を有し、上記相補的にドープされた壁(14、15)は、上記電荷補償領域(11)を形成し、
上記構造物(13)の相補的にドープされた壁(14、15)と、上記第2ドリフト領域(10)の充填用単結晶半導体材料(22)との間には、拡散阻害層(23)が設けられ、上記拡散阻害層(23)は、上記相補的にドープされた壁(14、15)又は上記充填用単結晶半導体材料(22)のうちの少なくとも一つに配置されるパワー半導体素子。 - 上記電流経路に対して横方向の上記電荷補償領域(11)の幅bKと、上記電流経路に対して横方向のドリフト領域(9、10)の幅bDとの間の比率vは、bK/bD=v≦0.1であることを特徴とする、請求項1に記載のパワー半導体素子。
- 上記電荷補償領域(11)の幅(bK)は、相補伝導型(10)ドーパントの第1ドリフト領域(n)ドリフト領域材料内に侵入される侵入深さによって決定され、上記侵入深さは、構造物(13)の壁領域(14、15)内に配置されており、上記構造物(13)は、第1伝導型(p)の単結晶半導体材料によって充填されていると共に上記電流経路の方向に伸びていることを特徴とする、請求項2に記載のパワー半導体素子。
- 上記電荷補償領域(11)の幅(bK)は、相補伝導型(p)単結晶半導体材料層の厚さによって決定され、上記相補伝導型(p)単結晶半導体材料層は、構造物(13)の壁領域(14、15)上に配置されており、上記構造物(13)は、第1伝導型(n)単結晶半導体材料によって充填されていると共に上記電流経路の方向に伸びていることを特徴とする、請求項2に記載のパワー半導体素子。
- 上記電荷補償領域(11)及び上記ドリフト領域(9、10)は、電極(6、7)間において、ストリップ型に互いに平行に配置されていることを特徴とする、請求項1〜4のいずれか1項に記載のパワー半導体素子。
- 各ストリップ型ドリフト領域(9、10)は、その幅(bD)を、上記電流経路の方向における2つのストリップ型電荷補償領域(11)によって、上記電流経路に対して横方向に制限されていることを特徴とする、請求項5に記載のパワー半導体素子。
- 上記半導体基材(4)は、高濃度にドープされた、第1伝導型(n)基板(12)又は相補伝導型(p)基板(12)を有し、上記基板上には、ドリフト経路(5)を有する、低濃度から中濃度にドープされた第1伝導型(n)エピタキシャル層(17)が配置されていることを特徴とする、請求項1〜6のいずれか1項に記載のパワー半導体素子。
- 上記電荷補償領域(11)は、その深さ(t)に関して、上記半導体基材(4)の上面(18)から、上記基板(12)の上面(19)まで伸びていることを特徴とする、請求項7に記載のパワー半導体素子。
- 上記半導体基材(4)は、上記ドリフト経路(5)と上記基板(12)との間に、パターン形成されていない低濃度にドープされた第1伝導型(n)下地エピタキシャル層(20)を有することを特徴とする、請求項1〜8のいずれか1項に記載のパワー半導体素子。
- 上記電荷補償領域(11)は、その深さ(t)に関して、上記半導体基材(4)の上面(18)から、上記下地エピタキシャル層(20)の上面(21)まで伸びていることを特徴とする、請求項9に記載のパワー半導体素子。
- 上記パワー半導体素子(1)は、電流方向に対して横方向の上記ドリフト経路(5)の領域においては、周囲の上記ドリフト領域(9、10)よりも高濃度にドープされた第1伝導型層を有し、電荷補償領域(11)の範囲においては、純濃度の低減された相補伝導型(p)置換欠陥を有すことを特徴とする、請求項1〜10のいずれか1項に記載のパワー半導体素子。
- 第1ドリフト領域(9)及び/又は第2ドリフト領域(10)は、第1伝導型(4)単結晶半導体材料(22)を有し、上記充填用単結晶半導体材料(22)には、不純物原子が、置換的及び/又は格子間に配置されることを特徴とする、請求項1〜11のいずれか1項に記載のパワー半導体素子。
- 上記第2ドリフト領域(10)は、相補的にドープされた壁(14、15)が設けられた構造物(13)内における、第1伝導型(n)単結晶半導体材料(22)を有し、置換的及び/又は格子間に配置された炭素濃度[C]は、[C]≦1×1020cm−3であることを特徴とする、請求項1〜12のいずれか1項に記載のパワー半導体素子。
- 上記第2ドリフト領域(10)は、相補的にドープされた壁(14、15)が設けられた構造物(13)内における、第1伝導型(n)単結晶半導体材料を有し、
上記構造物(13)は、完全には充填されておらず、かつ上記構造物(13)の上部領域内に絶縁材の端部充填物であるSiO2端部充填を有することを特徴とする、請求項1〜13のいずれか1項に記載のパワー半導体素子。 - 上記構造物(13)の相補的にドープされた壁(14、15)は、Si0.86Ge0.07C0.07を備える拡散阻害単結晶層(23)を、第2ドリフト領域(10)の充填用単結晶半導体材料(22)に対して有すことを特徴とする、請求項1〜14のいずれか1項に記載のパワー半導体素子。
- ゲルマニウム及び炭素が、シリコン結晶格子サイト上に置換的に配置されていることを特徴とする、請求項14に記載のパワー半導体素子。
- アモルファスシリコン、又は三次元の炭化ケイ素、又はシリコンゲルマニウムが、上記拡散阻害層(23)として設けられている、請求項1に記載のパワー半導体素子。
- 上記パワー半導体素子は、エッジ終端部として少なくとも1つのエッジトレンチ(25)を備えるエッジ構造物(24)を有することを特徴とする、請求項1〜17のいずれか1項に記載のパワー半導体素子。
- 上記エッジ構造物(24)は、上記パワー半導体素子(1)のエッジ(27)に沿った上記エッジトレンチ(25)の壁(14)のうちの、少なくとも1つの相補的にドープされたエッジ補償領域(26)を有し、隣接するエッジ(25)は、パワー半導体素子(1)のエッジ(27)に対して単結晶に成長させた半導体材料(22)を有することを特徴とする、請求項18に記載のパワー半導体素子。
- 上記エッジ構造物(24)は、上記パワー半導体素子(1)の上記エッジ(27)までのエッジ輪郭(28)を有し、上記エッジ輪郭は、上記エッジトレンチ(25)に成長されたエピタキシャル層(22)の湾曲された輪郭を有し、上記湾曲された輪郭は、上記半導体基材(4)の上面(18)から、上記単結晶半導体材料(22)の領域における基板(12)の中に垂直に伸びており、半導体層上には、上記エッジ輪郭(28)に適合するエッジパッシベーション層(29)が配置されていることを特徴とする、請求項19に記載のパワー半導体素子。
- 上記エッジパッシベーション層(29)は、半導体酸化物、半導体窒化物、DLC、熱成長酸化物、及び/又は炭化ケイ素を有することを特徴とする、請求項20に記載のパワー半導体素子。
- ドリフト経路における電荷補償領域を有さないパワー半導体素子は、エッジトレンチ(25)、エッジ補償領域(26)、及びエッジ輪郭パッシベーション層(29)を備えるエッジ構造物(24)を有することを特徴とする、請求項18〜21のいずれか1項に記載のパワー半導体素子。
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