JP2012138593A - 電荷補償構造を有するパワー半導体素子の製造方法 - Google Patents
電荷補償構造を有するパワー半導体素子の製造方法 Download PDFInfo
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- JP2012138593A JP2012138593A JP2012031071A JP2012031071A JP2012138593A JP 2012138593 A JP2012138593 A JP 2012138593A JP 2012031071 A JP2012031071 A JP 2012031071A JP 2012031071 A JP2012031071 A JP 2012031071A JP 2012138593 A JP2012138593 A JP 2012138593A
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/861—Diodes
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
【解決手段】半導体素子1は、2つの電極6、7間にドリフト経路5を備える半導体基材4を有し、ドリフト経路5は、ドリフト経路内の電極6、7間に電流経路を提供する第1伝導型ドリフト領域を含む。相補伝導型電荷補償領域11は、ドリフト経路5内の上記電流経路を制限する。このために、ドリフト経路5は、エピタキシャル法によって交互に成長させた2つの拡散領域型9、10を含み、第1ドリフト領域型9は、単結晶基板12上における単結晶半導体材料を有し、第2ドリフト領域型10は、相補的にドーピングされた壁14、15を有するトレンチ構造物13内における単結晶半導体材料を有する。壁14、15は、電荷補償領域11を形成する。
【選択図】図1
Description
せた後の、高濃度にドープされた基板を概略的に示す断面図である。
2 パワー半導体素子(第2実施形態)
3 電荷補償構造
4 半導体基材
5 ドリフト経路
6 ソース電極
7 ドレイン電極
8 ゲート電極
9 ドリフト領域、第1ドリフト領域型
10 ドリフト領域、第2ドリフト領域型
11 電荷補償領域
12 単結晶基板
13 トレンチ構造物
14 トレンチ構造物の壁
15 トレンチ構造物の壁
16 トレンチ構造物の壁上の相補伝導層
17 中濃度にドープされたエピタキシャル層
18 半導体基材の上面
19 基板の上面
20 下地エピタキシャル層
21 下地エピタキシャル層の上面
22 充填された単結晶半導体材料
23 拡散阻害層
24 エッジ構造物
25 エッジトレンチ
26 エッジ補償領域
27 パワー半導体素子のエッジ
28 エッジ輪郭
29 エッジパッシベーション層
30 トレンチ構造物の底部
31 半導体基材の背面
32 パターン形成された補助層
33 終点制御層
34 メサの上面
35 メサ
36 トレンチ構造物の壁上の高濃度にドープされた単結晶のエピタキシャル層
37 平らにしているフォトレジスト層
38 エッジ領域
39 p伝導型ボディー領域
40 破線
D ドレイン電極
G ゲート電極
S ソース電極
h 上記メサの高さ
t トレンチ深さ
W 上記エピタキシャル層の層厚
Claims (37)
- パワー半導体素子(1)の製造方法であって:
半導体基材(4)の基板(12)として、行及び列状に配置され、かつ複数のパワー半導体素子の区分を有する、高濃度にドープされた第1伝導型(n)半導体ウェハ又は相補伝導型(p)半導体ウェハを提供する工程;
第1ドリフト領域型(9)用のスターティングマテリアルとして、上記半導体ウェハ上に、第1伝導型(n)エピタキシャル層(17)を成長させる工程;
上記パワー半導体素子の区分にトレンチ構造物(13)を導入する工程;
電荷補償領域(11)用に、相補伝導型(p)ドーパント層によって上記トレンチ構造物の壁(14、15)をドーピングする工程;
上記トレンチ構造物(13)の底部(30)、及び第1ドリフト領域型(9)の上面(18)に異方性の除去エッチングを施す工程;及び
第2ドリフト領域型(10)用のスターティングマテリアルとして、上記トレンチ構造物(13)において、中濃度にドープされた第1伝導型(n)エピタキシャル層(22)を成長させる工程を含む、パワー半導体素子の製造方法。 - 請求項1に記載のパワー半導体素子の製造方法であって:
成長したドリフト領域型(9、10)の所まで、上記半導体ウェハの上面(18)を平坦化させて、平坦化された上面(18)を有する半導体基材(4)を形成する工程;
上記半導体基材(4)内及び/又は上記半導体基材(4)上に、上面構造物及び背面構造物を形成して、上記半導体ウェハの上記パワー半導体素子の区分に上記パワー半導体素子(1)を完成させる工程;及び
上記半導体ウェハを個々のパワー半導体素子(1)に分割する工程を追加的に含む、パワー半導体素子の製造方法。 - 上記半導体ウェハ上に上記第1伝導型(n)エピタキシャル層(17)を成長させる前に、低濃度にドープされた第1伝導型(n)下地エピタキシャル層(21)を成長させることを特徴とする、請求項1又は2に記載のパワー半導体素子の製造方法。
- 上記半導体ウェハ又は下地エピタキシャル層(21)上に、上記第1伝導型(n)エピタキシャル層(17)を成長させる前に、補助層(32)をエッチングされるトレンチ(13)領域にエピタキシャル法によって導入し、ここで上記補助層はエッチング停止を可能にし、かつ、好ましくはSixGey(x>y)又はSixGeyCz(x>yかつx>z)を有することを特徴とする、請求項1、2、又は3に記載のパワー半導体素子の製造方法。
- 上記補助層(32)の組成物は、0.86≦x≦1、y≦0.07、及びz≦0.07を満たすことを特徴とする、請求項4に記載のパワー半導体素子の製造方法。
- 上記半導体ウェハ上又は上記下地エピタキシャル層(21)上に、上記第1伝導型(n)エピタキシャル層(17)を成長させる前に、エッチングされるトレンチ(13)領域内にパターン形成された補助層(32)を堆積させ、ここで上記補助層はエッチング停止を可能にし、かつ好ましくは半導体酸化物又は半導体窒化物を有し、微細構造にエッチングされるトレンチ(13)領域内に上記補助層の構造物を堆積させ、ここで上記微細構造の横方向の単結晶過度成長は可能であることを特徴とする、請求項1、2、又は3に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)を上記第1伝導型(n)エピタキシャル層(17)内に導入するために、上記パワー半導体素子の区分内の上記ドリフト経路(5)領域内においてストリップ型パターンを備える上記半導体ウェハに、フォトリソグラフィック法によってエッチングマスクを施すことを特徴とする、請求項1〜6のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の導入のために、上記トレンチ構造物(13)に異方性エッチング及び/又は等方性エッチングを行うことを特徴とする、請求項1〜7のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の導入のために、異方性反応性イオンエッチングを行うことを特徴とする、請求項1〜8のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の導入のために、方向性プラズマエッチングを行うことを特徴とする、請求項1〜9のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の導入のために、終点検出を伴う方向性プラズマエッチングを行うことを特徴とする、請求項1〜10のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記フォトリソグラフィック法によるマスクを除去すると共に、上記半導体ウェハの上面に、上記トレンチ(13)間に形成されたメサ(35)を有する第1ドリフト領域型(9)を形成することを特徴とする、請求項1〜11のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記エッチングマスクを施す前に、好ましくは半導体酸化物、及び/又は、半導体窒化物、及び/又は、好ましくはSi0.86Ge0.07C0.07である、SixGeyCz層(x>yかつx>z)から成るパターン形成された終点制御層(33)を堆積させ、上記終点制御層は第1拡散領域型(9)の上面を覆うことを特徴とする、請求項1〜12のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の導入後、かつ上記トレンチ壁(14、15)のドーピング前に、上記トレンチ構造物(13)の表面を化学的に清浄することを特徴とする、請求項1〜13のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の導入後、かつ上記トレンチ壁(14、15)のドーピングの前に、上記半導体ウェハの表面を酸化させ、その後、この酸化層をエッチングにより除去することを特徴とする、請求項1〜14のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の導入後、かつトレンチ壁(14、15)のドーピング前に、上記トレンチ壁を水素熱処理工程によって平滑化させることを特徴とする、請求項1〜15のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の導入後、かつトレンチ壁(14、15)を相補伝導型(p)にドーピングする前に、上記メサ(35)における第1伝導型(n)の濃度を適合かつ増大させるために、上記メサ(35)を気相からドーピングすることを特徴とする、請求項1〜16のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物の壁(14、15)をドーピングして電荷補償領域(11)を形成するために、上記半導体ウェハ上に、比較的高濃度にドープされた相補伝導性単結晶層(36)をエピタキシャル法によって成長させることを特徴とする、請求項1〜17のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物の壁(14、15)をドーピングして電荷補償領域(11)を形成するための、比較的高濃度にドープされた相補伝導性単結晶層(36)を、100nm≦d≦1000nm間、好ましくは200nm≦d≦600nmである厚さdに成長させることを特徴とする、請求項1〜17のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物の壁(14、15)をドーピングして電荷補償領域(11)を形成するために、ドープされたガラス層を上記トレンチ構造物(13)の領域上に堆積させ、かつ拡散工程後、上記ガラス層を除去することを特徴とする、請求項1〜17のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物の壁(14、15)をドーピングして電荷補償領域(11)を形成するために、上記気相からのプレドーピングを、次のポスト拡散工程と共に行うことを特徴とする、請求項1〜17のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物の壁(14、15)をドーピングして電荷補償領域(11)を形成するために、トレンチ構造物(13)の領域上に原子層堆積法を、次の上記壁内への内方拡散と共に行うことを特徴とする、請求項1〜17のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物の壁(14、15)をドーピングして電荷補償領域(11)を形成した後、上記トレンチ構造物(13)の領域上に拡散阻害単結晶補助層(23)を堆積させ、上記補助層は、請求項1〜4のいずれか1項に係る構成及び組成物に関して提供されることを特徴とする、請求項1〜22のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物の壁(14、15)をドーピングして電荷補償領域(11)を形成した後、上記トレンチ構造物の領域上に、拡散阻害層(23)を10nm≦d≦300nm、好ましくは50nm≦d≦150nmの厚さに堆積させることを特徴とする、請求項1〜23のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)の底部(30)及び/又は第1ドリフト領域型(9)のメサ(35)の上面(34)に異方性の除去エッチングを施すために、請求項5〜8のいずれか1項に係るドライエッチング法を用いることを特徴とする、請求項1〜24のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)において中濃度にドープされた第1伝導型(n)エピタキシャル層(22)を成長させる前に、上記トレンチ壁(14、15)が斜面を有するように上記トレンチ壁をエッチングして、上記半導体基材(4)の上面(18)の幅を上記トレンチ構造物(13)の底部(30)の幅とほぼ同一にし、これによって上記トレンチ構造物が略樽形にアンダーカットされることを特徴とする、請求項1〜25のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)において中濃度にドープされた第1伝導型(n)エピタキシャル層(22)を成長させる前に、上記トレンチ壁(14、15)が斜面を有するように上記トレンチ壁をエッチングして、上記半導体基材(4)の上面(18)における上記トレンチ構造物(13)の幅を上記トレンチ構造物(13)の底部(30)におけるものよりも短くすることを特徴とする、請求項1〜25のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)において中濃度にドープされた第1伝導型(n)のエピタキシャル層(22)を成長させる前に、上記トレンチ壁(14、15)が斜面を有するように上記トレンチ壁をエッチングして、上記半導体基材(4)の上面(18)における上記トレンチ構造物(13)の幅を、上記トレンチ構造物(13)の底部(30)におけるものよりも長くすることを特徴とする、請求項1〜25のいずれか1項に記載のパワー半導体素子の製造方法。
- 第2ドリフト領域型(10)用のスターティングマテリアルとして、上記トレンチ構造物(13)において中濃度にドープされた第1伝導型(n)エピタキシャル層(17)を成長させるために、上記エピタキシャル材料を、[C]≦1×1020cm−3である濃度[C]まで炭素でドープすることを特徴とする、請求項1〜28のいずれか1項に記載のパワー半導体素子の製造方法。
- 第2ドリフト領域型(10)用のスターティングマテリアルとして、上記トレンチ構造物(13)において中濃度にドープされた第1伝導型(n)エピタキシャル層(17)を成長させる時、上記トレンチ構造物(13)をエピタキシャル材料(17)によって完全には充填せず、かつ酸化物充填物を上記トレンチ構造物(13)の終端部として提供することを特徴とする、請求項1〜29のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記トレンチ構造物(13)を真性伝導性ポリシリコンによって充填することを特徴とする、請求項1〜30のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記半導体の上面(19)を平坦化させて、平坦化された上面(18)を有する半導体基材(4)を形成するために、化学的機械研磨法(CMP)を用いることを特徴とする、請求項1〜31のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記半導体の上面(19)を平坦化させて、平坦化された上面(18)及び背面(31)を有する半導体基材(4)を形成するために、まず、水平化フォトレジスト層(37)又はスピンオンガラス層を、平坦でない上面(18)に堆積させ、選択されたエッチング法又は除去法に関して、上記ドリフトセル型半導体材料に対する上記エッチング選択因子をほぼ1とすることを特徴とする、請求項1〜27のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記成長されたドリフト領域型(9、10)まで、上記半導体ウェハの上面(18)を平坦化するために、堆積され、かつ平坦化されたフォトレジスト層(37)又はスピンオンガラス層、及び上記エピタキシャル材料をエッチングバックすることを特徴とする、請求項1〜33のいずれか1項に記載のパワー半導体素子の製造方法。
- 上記半導体ウェハを、350℃≦T≦500℃である温度Tにおいてアニーリングすると共に、上記半導体ウェハの上面(18)及び/又は背面(31)から、プロトン注入を行うことを特徴とする、請求項1〜34のいずれか1項に記載のパワー半導体素子の製造方法。
- パワー半導体素子内にn型ドープ領域を形成する、陽子加速器、特には線形加速器の使用。
- パワー半導体素子内の補償構造物において、n型ドープ領域を形成する、請求項35に記載の陽子加速器、特には線形加速器の使用。
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CN111855706B (zh) * | 2020-07-28 | 2023-08-15 | 哈尔滨工业大学 | 半导体材料辐射诱导位移缺陷的检测方法 |
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