JP5097997B2 - 配線素子ブロックとそれを含む半導体チップ - Google Patents

配線素子ブロックとそれを含む半導体チップ Download PDF

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Publication number
JP5097997B2
JP5097997B2 JP2009240551A JP2009240551A JP5097997B2 JP 5097997 B2 JP5097997 B2 JP 5097997B2 JP 2009240551 A JP2009240551 A JP 2009240551A JP 2009240551 A JP2009240551 A JP 2009240551A JP 5097997 B2 JP5097997 B2 JP 5097997B2
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wiring
layer
vdd
vss
wirings
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Japanese (ja)
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JP2010021574A (ja
JP2010021574A5 (enExample
Inventor
弘生 増田
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2009240551A 2009-10-19 2009-10-19 配線素子ブロックとそれを含む半導体チップ Expired - Fee Related JP5097997B2 (ja)

Priority Applications (1)

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JP2009240551A JP5097997B2 (ja) 2009-10-19 2009-10-19 配線素子ブロックとそれを含む半導体チップ

Applications Claiming Priority (1)

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JP2009240551A JP5097997B2 (ja) 2009-10-19 2009-10-19 配線素子ブロックとそれを含む半導体チップ

Related Parent Applications (1)

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JP2006231229A Division JP2006324701A (ja) 2006-08-28 2006-08-28 多層配線装置

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JP2010021574A JP2010021574A (ja) 2010-01-28
JP2010021574A5 JP2010021574A5 (enExample) 2010-04-15
JP5097997B2 true JP5097997B2 (ja) 2012-12-12

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JP2009240551A Expired - Fee Related JP5097997B2 (ja) 2009-10-19 2009-10-19 配線素子ブロックとそれを含む半導体チップ

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6366573B2 (ja) * 2012-04-30 2018-08-01 コーニンクレッカ フィリップス エヌ ヴェＫｏｎｉｎｋｌｉｊｋｅ Ｐｈｉｌｉｐｓ Ｎ．Ｖ． デカップリングにより毎ピクセル・アナログチャネルウェル絶縁された画像化検出器及び方法
US9520358B2 (en) * 2014-10-30 2016-12-13 Qualcomm Incorporated Via structure for optimizing signal porosity
US10318694B2 (en) * 2016-11-18 2019-06-11 Qualcomm Incorporated Adaptive multi-tier power distribution grids for integrated circuits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316323A (ja) * 1995-05-22 1996-11-29 Hitachi Ltd 電源配線の形成方法及びそれを用いた回路装置
JP3522144B2 (ja) * 1999-02-25 2004-04-26 富士通株式会社 容量回路および半導体集積回路装置
JP2001127162A (ja) * 1999-10-25 2001-05-11 Matsushita Electric Ind Co Ltd 半導体集積回路
JP3450258B2 (ja) * 2000-03-03 2003-09-22 Ｎｅｃエレクトロニクス株式会社 集積回路装置、回路製造方法

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JP2010021574A (ja) 2010-01-28

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