JP2010021574A5 - - Google Patents
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- Publication number
- JP2010021574A5 JP2010021574A5 JP2009240551A JP2009240551A JP2010021574A5 JP 2010021574 A5 JP2010021574 A5 JP 2010021574A5 JP 2009240551 A JP2009240551 A JP 2009240551A JP 2009240551 A JP2009240551 A JP 2009240551A JP 2010021574 A5 JP2010021574 A5 JP 2010021574A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- element block
- potentials
- wiring layer
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009240551A JP5097997B2 (ja) | 2009-10-19 | 2009-10-19 | 配線素子ブロックとそれを含む半導体チップ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009240551A JP5097997B2 (ja) | 2009-10-19 | 2009-10-19 | 配線素子ブロックとそれを含む半導体チップ |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006231229A Division JP2006324701A (ja) | 2006-08-28 | 2006-08-28 | 多層配線装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010021574A JP2010021574A (ja) | 2010-01-28 |
| JP2010021574A5 true JP2010021574A5 (enExample) | 2010-04-15 |
| JP5097997B2 JP5097997B2 (ja) | 2012-12-12 |
Family
ID=41706087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009240551A Expired - Fee Related JP5097997B2 (ja) | 2009-10-19 | 2009-10-19 | 配線素子ブロックとそれを含む半導体チップ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5097997B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2014148187A (ru) * | 2012-04-30 | 2016-06-27 | Конинклейке Филипс Н.В. | Детектор изображения с попиксельной изоляцией карманов аналоговых каналов с развязкой |
| US9520358B2 (en) * | 2014-10-30 | 2016-12-13 | Qualcomm Incorporated | Via structure for optimizing signal porosity |
| US10318694B2 (en) * | 2016-11-18 | 2019-06-11 | Qualcomm Incorporated | Adaptive multi-tier power distribution grids for integrated circuits |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08316323A (ja) * | 1995-05-22 | 1996-11-29 | Hitachi Ltd | 電源配線の形成方法及びそれを用いた回路装置 |
| JP3522144B2 (ja) * | 1999-02-25 | 2004-04-26 | 富士通株式会社 | 容量回路および半導体集積回路装置 |
| JP2001127162A (ja) * | 1999-10-25 | 2001-05-11 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
| JP3450258B2 (ja) * | 2000-03-03 | 2003-09-22 | Necエレクトロニクス株式会社 | 集積回路装置、回路製造方法 |
-
2009
- 2009-10-19 JP JP2009240551A patent/JP5097997B2/ja not_active Expired - Fee Related
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