JP2013229470A5 - - Google Patents
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- Publication number
- JP2013229470A5 JP2013229470A5 JP2012100976A JP2012100976A JP2013229470A5 JP 2013229470 A5 JP2013229470 A5 JP 2013229470A5 JP 2012100976 A JP2012100976 A JP 2012100976A JP 2012100976 A JP2012100976 A JP 2012100976A JP 2013229470 A5 JP2013229470 A5 JP 2013229470A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- region
- wirings
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 claims 26
- 239000010410 layer Substances 0.000 claims 21
- 239000004020 conductor Substances 0.000 claims 3
- 239000011229 interlayer Substances 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 230000000149 penetrating effect Effects 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012100976A JP2013229470A (ja) | 2012-04-26 | 2012-04-26 | 半導体装置及びそのレイアウト方法 |
| US13/800,782 US9059165B2 (en) | 2012-04-26 | 2013-03-13 | Semiconductor device having mesh-pattern wirings |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012100976A JP2013229470A (ja) | 2012-04-26 | 2012-04-26 | 半導体装置及びそのレイアウト方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013229470A JP2013229470A (ja) | 2013-11-07 |
| JP2013229470A5 true JP2013229470A5 (enExample) | 2015-05-28 |
Family
ID=49476576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012100976A Withdrawn JP2013229470A (ja) | 2012-04-26 | 2012-04-26 | 半導体装置及びそのレイアウト方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9059165B2 (enExample) |
| JP (1) | JP2013229470A (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102349417B1 (ko) | 2015-07-16 | 2022-01-10 | 삼성전자 주식회사 | 전압 강하를 개선할 수 있는 구조를 갖는 반도체 장치와 이를 포함하는 장치 |
| JP7200066B2 (ja) * | 2019-08-22 | 2023-01-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR20220015207A (ko) * | 2020-07-30 | 2022-02-08 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| KR102879037B1 (ko) | 2020-08-19 | 2025-10-29 | 삼성전자주식회사 | 복수개의 패턴들을 포함하는 반도체 소자 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5410107A (en) * | 1993-03-01 | 1995-04-25 | The Board Of Trustees Of The University Of Arkansas | Multichip module |
| JP2001127162A (ja) | 1999-10-25 | 2001-05-11 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
-
2012
- 2012-04-26 JP JP2012100976A patent/JP2013229470A/ja not_active Withdrawn
-
2013
- 2013-03-13 US US13/800,782 patent/US9059165B2/en active Active
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