JP5097306B2 - Dramメモリ素子のトランジスタ構造及びその製造方法 - Google Patents
Dramメモリ素子のトランジスタ構造及びその製造方法 Download PDFInfo
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- JP5097306B2 JP5097306B2 JP2012139562A JP2012139562A JP5097306B2 JP 5097306 B2 JP5097306 B2 JP 5097306B2 JP 2012139562 A JP2012139562 A JP 2012139562A JP 2012139562 A JP2012139562 A JP 2012139562A JP 5097306 B2 JP5097306 B2 JP 5097306B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 229910008484 TiSi Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
Description
11a、111a、211a 活性領域
2、12、112、212 フィールド膜
3、13、113、213 ゲート絶縁膜
4、14、114、214 ゲート電極
214a 第1導電膜
214b 第2導電膜
Claims (16)
- 半導体基板の所定の領域から突出した活性領域と、
前記活性領域内のチャネル領域に形成された凹溝部と、
前記半導体基板上に、前記凹溝部の底面より低い位置にある表面を有するように形成されたフィールド膜と、
前記凹溝部の底面および側壁と、前記フィールド膜によって露出した前記活性領域の側面とに形成されたゲート絶縁膜と、
前記ゲート絶縁膜が形成された前記凹溝部及び前記フィールド膜を横切るように形成されたゲート電極と、
前記ゲート電極の両側の前記活性領域に形成されたソース及びドレーン領域とを備えることを特徴とするDRAMメモリ素子のトランジスタ構造。 - 前記ゲート電極は、ポリゲート電極、又は低抵抗ゲート電極であることを特徴とする請求項1に記載のDRAMメモリ素子のトランジスタ構造。
- 前記低抵抗ゲート電極は、ポリシリコンからなる第1導電膜上に低抵抗材料からなる第2導電膜が更に形成された積層構造を有することを特徴とする請求項2に記載のDRAMメモリ素子のトランジスタ構造。
- 前記第2導電膜は、W、WN、WSix、及びTiSixからなるグループの中から選択されたいずれか1つの材料で形成されることを特徴とする請求項3に記載のDRAMメモリ素子のトランジスタ構造。
- 半導体基板をエッチングして、前記半導体基板の所定の領域から突出した活性領域を形成する第1ステップと、
前記半導体基板上に前記活性領域を画定するフィールド膜を形成する第2ステップと、
前記活性領域内のチャネル領域をエッチングして凹溝部を形成する第3ステップと、
前記凹溝部の底面より低い位置にある表面を有するように前記フィールド膜をエッチングする第4ステップと、
前記凹溝部の底面および側壁と、前記フィールド膜によって露出した前記活性領域の側面とにゲート絶縁膜を形成する第5ステップと、
前記ゲート絶縁膜が形成された前記凹溝部及び前記フィールド膜を横切るようにゲート電極を形成する第6ステップと、
前記ゲート電極の両側の前記活性領域にソース及びドレーン領域を形成する第7ステップとを含むことを特徴とするDRAMメモリ素子のトランジスタの製造方法。 - 前記第3ステップの後に前記第4ステップが実行される、又は、前記第4ステップの後に前記第3ステップが実行されることを特徴とする請求項5に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記第2ステップにおいて、前記フィールド膜は、2000〜6000Åの厚さで形成されることを特徴とする請求項5に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記凹溝部は、前記第2ステップで形成された前記フィールド膜の厚さの1/3の深さで形成されることを特徴とする請求項5に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記第4ステップにおいて、前記フィールド膜は、前記第2ステップで形成された前記フィールド膜の厚さの1/3に相当する膜が残存するようにエッチングされることを特徴とする請求項5に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記ゲート電極は、ポリゲート電極、又は低抵抗ゲート電極で形成されることを特徴とする請求項5に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記ゲート電極が低抵抗ゲート電極の場合、前記第6ステップは、前記ゲート絶縁膜及び前記フィールド膜の上にポリシリコンの第1導電膜を形成するステップと、前記第1導電膜を平坦化するステップと、平坦化した前記第1導電膜上に低抵抗材料の第2導電膜を形成するステップと、前記第1導電膜及び前記第2導電膜の所定の部分を順次エッチングするステップとを含むことを特徴とする請求項10に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記第2導電膜は、W、WN、WSix、及びTiSixからなるグループの中から選択されたいずれか1つの材料で形成されることを特徴とする請求項11に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記第2導電膜は、CVD、または、PVD法により形成されることを特徴とする請求項12に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記第1導電膜は、前記第4ステップの完了後に露出した前記活性領域の上部の高さ以上の厚さで形成されることを特徴とする請求項に11記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記第1導電膜は、前記活性領域の上に300〜1500Åの厚さの前記第1導電膜が残存するように平坦化されることを特徴とする請求項11に記載のDRAMメモリ素子のトランジスタの製造方法。
- 前記第1導電膜は、CMPによって平坦化されることを特徴とする請求項11に記載のDRAMメモリ素子のトランジスタの製造方法。
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KR10-2005-0036056 | 2005-04-29 | ||
KR1020050036056A KR100691006B1 (ko) | 2005-04-29 | 2005-04-29 | 메모리 소자의 셀 트랜지스터 구조 및 그 제조방법 |
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JP2012139562A Active JP5097306B2 (ja) | 2005-04-29 | 2012-06-21 | Dramメモリ素子のトランジスタ構造及びその製造方法 |
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JP (2) | JP2006310718A (ja) |
KR (1) | KR100691006B1 (ja) |
CN (1) | CN100456495C (ja) |
DE (1) | DE102005031702B4 (ja) |
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JP2012209572A (ja) | 2012-10-25 |
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KR100691006B1 (ko) | 2007-03-09 |
US7601583B2 (en) | 2009-10-13 |
US20080096355A1 (en) | 2008-04-24 |
DE102005031702A1 (de) | 2006-11-02 |
US7332755B2 (en) | 2008-02-19 |
JP2006310718A (ja) | 2006-11-09 |
TW200638470A (en) | 2006-11-01 |
TWI261303B (en) | 2006-09-01 |
CN100456495C (zh) | 2009-01-28 |
CN1855539A (zh) | 2006-11-01 |
DE102005031702B4 (de) | 2012-06-21 |
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