JP5091916B2 - 配線基板及び半導体装置 - Google Patents
配線基板及び半導体装置 Download PDFInfo
- Publication number
- JP5091916B2 JP5091916B2 JP2009138835A JP2009138835A JP5091916B2 JP 5091916 B2 JP5091916 B2 JP 5091916B2 JP 2009138835 A JP2009138835 A JP 2009138835A JP 2009138835 A JP2009138835 A JP 2009138835A JP 5091916 B2 JP5091916 B2 JP 5091916B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- solder
- pad
- wiring pattern
- substrate body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009138835A JP5091916B2 (ja) | 2009-06-10 | 2009-06-10 | 配線基板及び半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009138835A JP5091916B2 (ja) | 2009-06-10 | 2009-06-10 | 配線基板及び半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010287646A JP2010287646A (ja) | 2010-12-24 |
| JP2010287646A5 JP2010287646A5 (https=) | 2012-06-07 |
| JP5091916B2 true JP5091916B2 (ja) | 2012-12-05 |
Family
ID=43543154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009138835A Expired - Fee Related JP5091916B2 (ja) | 2009-06-10 | 2009-06-10 | 配線基板及び半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5091916B2 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101740878B1 (ko) * | 2011-03-22 | 2017-05-26 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치 |
| JP2013236039A (ja) * | 2012-05-11 | 2013-11-21 | Renesas Electronics Corp | 半導体装置 |
| JP6251828B2 (ja) * | 2017-01-30 | 2017-12-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04255291A (ja) * | 1991-02-07 | 1992-09-10 | Nec Corp | 印刷配線板 |
| JP4150511B2 (ja) * | 2001-05-16 | 2008-09-17 | 株式会社日立製作所 | 半導体レ−ザ装置 |
| JP3877642B2 (ja) * | 2002-05-21 | 2007-02-07 | ローム株式会社 | 半導体チップを使用した半導体装置 |
| JP2008047761A (ja) * | 2006-08-18 | 2008-02-28 | Ricoh Printing Systems Ltd | 半導体レーザ装置 |
| JP2008060159A (ja) * | 2006-08-29 | 2008-03-13 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP5018155B2 (ja) * | 2007-03-16 | 2012-09-05 | 富士通セミコンダクター株式会社 | 配線基板、電子部品の実装構造、及び半導体装置 |
| JP2009105139A (ja) * | 2007-10-22 | 2009-05-14 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法と半導体装置 |
-
2009
- 2009-06-10 JP JP2009138835A patent/JP5091916B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010287646A (ja) | 2010-12-24 |
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