JP5063398B2 - フロントコンタクトを有するパッケージ化された半導体発光デバイスを圧縮成形により形成する方法 - Google Patents
フロントコンタクトを有するパッケージ化された半導体発光デバイスを圧縮成形により形成する方法 Download PDFInfo
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- B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
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- B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C33/00—Moulds or cores; Details thereof or accessories therefor
- B29C33/02—Moulds or cores; Details thereof or accessories therefor with incorporated heating or cooling means
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- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29L—INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
- B29L2011/00—Optical elements, e.g. lenses, prisms
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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Description
Claims (18)
- 半導体発光デバイスをパッケージ化する方法であって、
前面の上に前記半導体発光デバイスおよびコンタクトを有する基板を設けるステップであって、前記半導体発光デバイスは、前記基板の前記前面の上の前記コンタクトと電気的に接続されるステップと、
前記基板の前記前面の上の前記半導体発光デバイスの上を覆う光学要素と、前記基板の前記前面の前記コンタクトを含む領域の上を覆う残余コーティングとを圧縮成形するステップと、
前記コンタクトに損傷を与えずに少なくとも前記コンタクトの一部分の上を覆う前記残余コーティングを除去するステップと
を含むことを特徴とする記載の方法。 - 前記基板を設けるステップは、
前記基板の前記前面の上に前記半導体発光デバイスを備え付けるステップと、
前記半導体発光デバイスを前記基板のコンタクト部分に電気的に接続するワイヤボンドを取り付けるステップと
を含むことを特徴とする請求項1に記載の方法。 - 前記基板の背面の上に第2の半導体発光デバイスを備え付けるステップと、
前記第2の半導体発光デバイスを前記基板の前記背面の上のコンタクトに電気的に接続するステップと
をさらに含むことを特徴とする請求項2に記載の方法。 - 前記圧縮成形するステップは、前記基板を圧縮成形して前記半導体発光デバイス及び前記ワイヤボンドの上を覆う前記光学要素を形成し、前記ワイヤボンドと直接に接触させるステップを含むことを特徴とする請求項2に記載の方法。
- 前記基板は、セラミック基板、メタルコアプリント回路基板(MCPCB)、可撓性回路基板、および/またはリードフレームを備えることを特徴とする請求項1に記載の方法。
- 前記圧縮成形するステップに先行して、前記前面側のコンタクトを覆うマスクを設けるステップが行われ、
前記残余コーティングを除去するステップは、前記マスクを除去するステップを含むことを特徴とする請求項1に記載の方法。 - 前記マスクは、ポリイミドフィルムを備えることを特徴とする請求項6に記載の方法。
- 前記マスクを除去するステップは、
前記マスクに対応するパターンに前記残余コーティングをカットするステップと、
前記マスク及び前記マスクに覆い重なっている前記残余コーティングを除去して、前記前面側のコンタクトを露出させるステップと
を含むことを特徴とする請求項6に記載の方法。 - 前記基板は、前記前面の上に複数の半導体発光デバイス及び複数のコンタクトを備え、
前記圧縮成形するステップは、前記基板を圧縮成形して、前記基板の前記前面の上に前記半導体発光デバイスの対応したそれぞれを覆う複数の光学要素と、前記基板の前記前面の上の前記複数のコンタクトを含む領域を覆う残余コーティングとを形成するステップを含み、
前記残余コーティングをカットするステップは、ホットナイフを用いて前記残余コーティングをカットするステップであって、前記ホットナイフは、前記残余コーティングの中にカットされたパターンに対応する2次元パターンを有し、
前記残余コーティングをカットするステップは、前記残余コーティングの中への前記ホットナイフの単一方向の動きによって前記残余コーティングをカットするステップを含む
ことを特徴とする請求項8に記載の方法。 - 前記光学要素は、レンズを備え、
前記圧縮成形するステップは、
前記複数の半導体発光デバイスの対応したそれぞれの近傍に位置する複数のレンズ形状のキャビティを備える鋳型の中に前記基板を配置するステップと、
前記鋳型の中にシリコーンを供給するステップと、
前記キャビティの中の前記シリコーンから前記レンズを圧縮成形するステップと、
前記鋳型の中で形成された前記レンズを有する前記基板を前記鋳型から取り外すステップと
を含むことを特徴とする請求項9に記載の方法。 - 前記シリコーンを提供するステップに先行して、前記キャビティを備える前記鋳型の表面上に剥離層を設けるステップが行われ、
前記基板を取り外すステップは、前記剥離層のところで前記基板を取り外すステップを含むことを特徴とする請求項10に記載の方法。 - 前記基板は、可撓性回路基板を備え、
前記残余コーティングを除去するステップは、前記基板を湿式溶媒で化学洗浄して前記コンタクトの上を覆う前記残余コーティングを除去するステップを含むことを特徴とする請求項1に記載の方法。 - 前記基板は、前記前面の上に複数の半導体発光デバイス及び複数のコンタクトを備え、
前記基板を圧縮成形するステップは、前記基板を圧縮成形して、前記基板の前記前面の上に前記半導体発光デバイスの対応したそれぞれを覆う複数の光学要素と、前記基板の前記前面の前記複数のコンタクトを含む領域を覆う残余コーティングとを形成するステップを含むことを特徴とする請求項12に記載の方法。 - 前記光学要素は、レンズを備え、
前記圧縮成形するステップは、
前記複数の半導体発光デバイスの対応したそれぞれの近傍に位置する複数のレンズ形状のキャビティを備える鋳型の中に前記基板を配置するステップと、
前記鋳型の中にシリコーンを供給するステップと、
前記キャビティの中の前記シリコーンから前記レンズを圧縮成形するステップと、
前記鋳型の中に形成された前記レンズを有する前記基板を前記鋳型から取り外すステップと
を含むことを特徴とする請求項13に記載の方法。 - 前記光学要素は、第1の光学要素および第2の光学要素を備え、
前記圧縮成形するステップは、
前記半導体発光デバイスの近傍に前記第1の光学要素を圧縮成形するステップと、
前記半導体発光デバイス及び前記第1の光学要素の上を覆って前記第2の光学要素を圧縮成形するステップと
を含むことを特徴とする請求項1に記載の方法。 - 前記第1の光学要素を圧縮成形するステップは、前記半導体発光デバイスの上を覆って前記第1の光学要素を圧縮成形するステップを含むことを特徴とする請求項15に記載の方法。
- 前記光学要素は、第2の光学要素を備え、前記圧縮成形するステップに先行して前記半導体発光デバイスの近傍に第1の光学要素を形成するステップを行い、
前記基板を圧縮成形するステップは、前記半導体発光デバイス及び前記第1の光学要素の上を覆って前記第2の光学要素を圧縮成形するステップを含むことを特徴とする請求項1に記載の方法。 - 前記光学要素は、第1の光学要素を備え、
前記半導体発光デバイス及び前記第1の光学要素の上を覆って第2の光学要素を形成するステップを、前記圧縮成形するステップの後に行うことを特徴とする請求項1に記載の方法。
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US11/705,233 US9061450B2 (en) | 2007-02-12 | 2007-02-12 | Methods of forming packaged semiconductor light emitting devices having front contacts by compression molding |
US11/705,233 | 2007-02-12 |
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US9061450B2 (en) | 2015-06-23 |
US8822245B2 (en) | 2014-09-02 |
US8669573B2 (en) | 2014-03-11 |
JP2008205462A (ja) | 2008-09-04 |
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