JP5063113B2 - 半導体構造、二重仕事関数のｃｍｏｓデバイス、二重仕事関数のｃｍｏｓ回路、および基板上に二重仕事関数のｃｍｏｓデバイスを形成する方法（炭化金属ゲート構造および形成方法） - Google Patents

半導体構造、二重仕事関数のｃｍｏｓデバイス、二重仕事関数のｃｍｏｓ回路、および基板上に二重仕事関数のｃｍｏｓデバイスを形成する方法（炭化金属ゲート構造および形成方法） Download PDF

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JP5063113B2
JP5063113B2 JP2006541483A JP2006541483A JP5063113B2 JP 5063113 B2 JP5063113 B2 JP 5063113B2 JP 2006541483 A JP2006541483 A JP 2006541483A JP 2006541483 A JP2006541483 A JP 2006541483A JP 5063113 B2 JP5063113 B2 JP 5063113B2
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carbon
metal
work function
layer
containing layer
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JP2007525827A5 (enExample
JP2007525827A (ja
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カブラル、シリル
デタヴァーニア、クリストファー
ジャミー、ラジャラオ
ゼンガー、キャサリン、エル
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Physical Vapour Deposition (AREA)
JP2006541483A 2003-11-28 2004-11-29 半導体構造、二重仕事関数のｃｍｏｓデバイス、二重仕事関数のｃｍｏｓ回路、および基板上に二重仕事関数のｃｍｏｓデバイスを形成する方法（炭化金属ゲート構造および形成方法） Expired - Fee Related JP5063113B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/722,557 2003-11-28
US10/722,557 US7064050B2 (en) 2003-11-28 2003-11-28 Metal carbide gate structure and method of fabrication
PCT/US2004/039855 WO2005062752A2 (en) 2003-11-28 2004-11-29 Metal carbide gate structure and method of fabrication

Publications (3)

Publication Number Publication Date
JP2007525827A JP2007525827A (ja) 2007-09-06
JP2007525827A5 JP2007525827A5 (enExample) 2007-12-27
JP5063113B2 true JP5063113B2 (ja) 2012-10-31

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US (2) US7064050B2 (enExample)
EP (1) EP1687457B1 (enExample)
JP (1) JP5063113B2 (enExample)
KR (1) KR100956714B1 (enExample)
CN (1) CN101151724B (enExample)
AT (1) ATE460746T1 (enExample)
DE (1) DE602004025966D1 (enExample)
TW (1) TWI374516B (enExample)
WO (1) WO2005062752A2 (enExample)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7226826B2 (en) * 2004-04-16 2007-06-05 Texas Instruments Incorporated Semiconductor device having multiple work functions and method of manufacture therefor
DE102004030552B4 (de) * 2004-06-24 2008-12-24 Qimonda Ag Schicht-Anordnung, Feldeffekttransistor und Verfahren zum Herstellen einer Schicht-Anordnung
US7514310B2 (en) * 2004-12-01 2009-04-07 Samsung Electronics Co., Ltd. Dual work function metal gate structure and related method of manufacture
JP4764030B2 (ja) * 2005-03-03 2011-08-31 株式会社東芝 半導体装置及びその製造方法
GB2424312B (en) * 2005-03-14 2010-03-03 Denso Corp Method of forming an ohmic contact in wide band semiconductor
JP4607645B2 (ja) * 2005-04-04 2011-01-05 株式会社東芝 半導体装置及びその製造方法
JP4557879B2 (ja) * 2005-12-09 2010-10-06 株式会社東芝 半導体装置及びその製造方法
JP2007214436A (ja) * 2006-02-10 2007-08-23 Tokyo Electron Ltd 半導体装置の製造方法および半導体装置
US20080272435A1 (en) * 2007-05-02 2008-11-06 Chien-Ting Lin Semiconductor device and method of forming the same
JP5414053B2 (ja) * 2007-12-07 2014-02-12 独立行政法人物質・材料研究機構 金属電極及びこれを用いた半導体素子
US7781321B2 (en) 2008-05-09 2010-08-24 International Business Machines Corporation Electroless metal deposition for dual work function
US8927057B2 (en) * 2010-02-22 2015-01-06 International Business Machines Corporation Graphene formation utilizing solid phase carbon sources
US8574990B2 (en) 2011-02-24 2013-11-05 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gate
US8802524B2 (en) 2011-03-22 2014-08-12 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gates
JP2012204689A (ja) * 2011-03-25 2012-10-22 Toshiba Corp 半導体装置及びその製造方法
US8704294B2 (en) 2011-06-13 2014-04-22 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US8486790B2 (en) 2011-07-18 2013-07-16 United Microelectronics Corp. Manufacturing method for metal gate
US8477006B2 (en) 2011-08-30 2013-07-02 United Microelectronics Corp. Resistor and manufacturing method thereof
US8765588B2 (en) 2011-09-28 2014-07-01 United Microelectronics Corp. Semiconductor process
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
US8546212B2 (en) 2011-12-21 2013-10-01 United Microelectronics Corp. Semiconductor device and fabricating method thereof
US8860181B2 (en) 2012-03-07 2014-10-14 United Microelectronics Corp. Thin film resistor structure
US8951855B2 (en) 2012-04-24 2015-02-10 United Microelectronics Corp. Manufacturing method for semiconductor device having metal gate
US9054172B2 (en) 2012-12-05 2015-06-09 United Microelectrnics Corp. Semiconductor structure having contact plug and method of making the same
US8735269B1 (en) 2013-01-15 2014-05-27 United Microelectronics Corp. Method for forming semiconductor structure having TiN layer
US9129985B2 (en) 2013-03-05 2015-09-08 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US9219078B2 (en) 2013-04-18 2015-12-22 International Business Machines Corporation Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
US9184254B2 (en) 2013-05-02 2015-11-10 United Microelectronics Corporation Field-effect transistor and fabricating method thereof
US9159798B2 (en) 2013-05-03 2015-10-13 United Microelectronics Corp. Replacement gate process and device manufactured using the same
US9196542B2 (en) 2013-05-22 2015-11-24 United Microelectronics Corp. Method for manufacturing semiconductor devices
US8921947B1 (en) 2013-06-10 2014-12-30 United Microelectronics Corp. Multi-metal gate semiconductor device having triple diameter metal opening
US9196546B2 (en) 2013-09-13 2015-11-24 United Microelectronics Corp. Metal gate transistor
US9741577B2 (en) 2015-12-02 2017-08-22 International Business Machines Corporation Metal reflow for middle of line contacts
US9960078B1 (en) 2017-03-23 2018-05-01 International Business Machines Corporation Reflow interconnect using Ru
US10672649B2 (en) 2017-11-08 2020-06-02 International Business Machines Corporation Advanced BEOL interconnect architecture
US10541199B2 (en) 2017-11-29 2020-01-21 International Business Machines Corporation BEOL integration with advanced interconnects
TWI801222B (zh) * 2022-04-26 2023-05-01 國立成功大學 多元合金材料層、其製造方法及半導體裝置的電容結構
US11888159B1 (en) * 2023-02-10 2024-01-30 Lyten, Inc. Material and method for increasing catalytic activity of electrocatalysts

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2552159B2 (ja) * 1987-02-02 1996-11-06 セイコーエプソン株式会社 半導体装置及びその製造方法
JPH0231462A (ja) * 1988-07-20 1990-02-01 Sharp Corp 半導体素子
JPH02155271A (ja) * 1988-12-07 1990-06-14 Toshiba Corp 半導体装置
CA2014296C (en) * 1989-04-21 2000-08-01 Nobuo Mikoshiba Integrated circuit
JPH02296141A (ja) * 1989-05-10 1990-12-06 Terumo Corp 機能性素子及びそれを備えたｆｅｔセンサ
US5294822A (en) * 1989-07-10 1994-03-15 Texas Instruments Incorporated Polycide local interconnect method and structure
JP2881267B2 (ja) * 1991-01-11 1999-04-12 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2657588B2 (ja) * 1991-01-11 1997-09-24 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置およびその作製方法
US6344663B1 (en) * 1992-06-05 2002-02-05 Cree, Inc. Silicon carbide CMOS devices
US5384470A (en) * 1992-11-02 1995-01-24 Kobe Steel, Usa, Inc. High temperature rectifying contact including polycrystalline diamond and method for making same
JP3315541B2 (ja) * 1994-11-04 2002-08-19 新日本無線株式会社 ＳｉＣへの電極の形成方法
KR0147626B1 (ko) 1995-03-30 1998-11-02 김광호 타이타늄 카본 나이트라이드 게이트전극 형성방법
DE19525069C1 (de) * 1995-07-10 1996-10-24 Siemens Ag Verfahren zur Herstellung einer integrierten CMOS-Schaltung
US6028339A (en) * 1996-08-29 2000-02-22 International Business Machines Corporation Dual work function CMOS device
US5770490A (en) * 1996-08-29 1998-06-23 International Business Machines Corporation Method for producing dual work function CMOS device
US6936849B1 (en) * 1997-07-29 2005-08-30 Micron Technology, Inc. Silicon carbide gate transistor
US6261887B1 (en) * 1997-08-28 2001-07-17 Texas Instruments Incorporated Transistors with independently formed gate structures and method
US6087225A (en) * 1998-02-05 2000-07-11 International Business Machines Corporation Method for dual gate oxide dual workfunction CMOS
US6492694B2 (en) * 1998-02-27 2002-12-10 Micron Technology, Inc. Highly conductive composite polysilicon gate for CMOS integrated circuits
US6027961A (en) * 1998-06-30 2000-02-22 Motorola, Inc. CMOS semiconductor devices and method of formation
KR100280102B1 (ko) * 1998-10-13 2001-03-02 윤덕용 코발트-카본 합금박막을 이용한 단결정 코발트다이실리사이드콘택 형성방법
US6291282B1 (en) * 1999-02-26 2001-09-18 Texas Instruments Incorporated Method of forming dual metal gate structures or CMOS devices
US6492688B1 (en) * 1999-03-02 2002-12-10 Siemens Aktiengesellschaft Dual work function CMOS device
US6194748B1 (en) * 1999-05-03 2001-02-27 Advanced Micro Devices, Inc. MOSFET with suppressed gate-edge fringing field effect
JP3906020B2 (ja) * 2000-09-27 2007-04-18 株式会社東芝 半導体装置及びその製造方法
JP2002217313A (ja) * 2000-11-30 2002-08-02 Texas Instruments Inc 金属及び対応する金属珪化物から形成した各ゲートを有する相補形トランジスタ
KR100399356B1 (ko) * 2001-04-11 2003-09-26 삼성전자주식회사 듀얼 게이트를 가지는 씨모스형 반도체 장치 형성 방법
US6664589B2 (en) * 2001-08-30 2003-12-16 Micron Technology, Inc. Technique to control tunneling currents in DRAM capacitors, cells, and devices
US6653698B2 (en) * 2001-12-20 2003-11-25 International Business Machines Corporation Integration of dual workfunction metal gate CMOS devices
US6794234B2 (en) * 2002-01-30 2004-09-21 The Regents Of The University Of California Dual work function CMOS gate technology based on metal interdiffusion
JP2004228547A (ja) * 2002-11-29 2004-08-12 Sony Corp 半導体装置およびその製造方法
US6858524B2 (en) * 2002-12-03 2005-02-22 Asm International, Nv Method of depositing barrier layer for metal gates
US7122414B2 (en) * 2002-12-03 2006-10-17 Asm International, Inc. Method to fabricate dual metal CMOS devices
US7138685B2 (en) * 2002-12-11 2006-11-21 International Business Machines Corporation Vertical MOSFET SRAM cell
JP2004200550A (ja) * 2002-12-20 2004-07-15 Renesas Technology Corp 半導体装置の製造方法
US6933222B2 (en) * 2003-01-02 2005-08-23 Intel Corporation Microcircuit fabrication and interconnection
US6972224B2 (en) * 2003-03-27 2005-12-06 Freescale Semiconductor, Inc. Method for fabricating dual-metal gate device
US20050049954A1 (en) * 2003-09-03 2005-03-03 Graham Russell J. Portfolio compliance managing techniques
US7148546B2 (en) * 2003-09-30 2006-12-12 Texas Instruments Incorporated MOS transistor gates with doped silicide and methods for making the same
US20050095763A1 (en) * 2003-10-29 2005-05-05 Samavedam Srikanth B. Method of forming an NMOS transistor and structure thereof
US7129182B2 (en) * 2003-11-06 2006-10-31 Intel Corporation Method for etching a thin metal layer
US6869889B1 (en) * 2004-04-07 2005-03-22 Intel Corporation Etching metal carbide films

Also Published As

Publication number Publication date
TW200524089A (en) 2005-07-16
CN101151724B (zh) 2012-02-01
EP1687457B1 (en) 2010-03-10
WO2005062752A2 (en) 2005-07-14
ATE460746T1 (de) 2010-03-15
TWI374516B (en) 2012-10-11
US7064050B2 (en) 2006-06-20
WO2005062752A3 (en) 2007-05-18
DE602004025966D1 (de) 2010-04-22
KR100956714B1 (ko) 2010-05-06
EP1687457A2 (en) 2006-08-09
US7667278B2 (en) 2010-02-23
EP1687457A4 (en) 2009-06-17
CN101151724A (zh) 2008-03-26
US20060186490A1 (en) 2006-08-24
US20050116230A1 (en) 2005-06-02
KR20070008528A (ko) 2007-01-17
JP2007525827A (ja) 2007-09-06

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